The pySVModel Documentation¶

An abstract System Verilog language model.

Main Goals¶

This package provides a unified abstract language model for System Verilog (incl. Verilog). Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.

Projects consuming pre-processed System Verilog data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.

Use Cases¶

TBD

News¶

Sep. 2021 - New Repository Created¶

Moved VerilogVersion and SystemVerilogVersion classes from pyEDAA.ProjectModel to this new repository.

Contributors¶

License¶

This Python package (source code) is licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).

This document was generated on 12.Jan 2024 - 00:39.