Glossary

Accellera

Accellera Systems Initiative

Accellera Systems Initiative is the standards organization of the electronic design automation industry, formed from Open Verilog International (OVI) and VHDL International, later joined by The SPIRIT Consortium and the Open SystemC Initiative (OSCI).

Accellera developed SystemVerilog up to version 3.1a and handed it over to the IEEE, which standardized it as IEEE Std. 1800.

HDL

Hardware Description Language

A language describing the structure and behavior of digital circuits, for simulation and synthesis, e.g. Verilog or VHDL.

Wikipedia: Hardware description language

IEEE

The Institute of Electrical and Electronics Engineers. Its standards association IEEE SA publishes the LRMs of Verilog (IEEE Std. 1364) and SystemVerilog (IEEE Std. 1800).

LRM

Language Reference Manual

The standard defining a language’s syntax and semantics.

IEEE Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language:

• 1800-2023.

• 1800-2017.

• 1800-2012.

• 1800-2009.

• 1800-2005.

IEEE Standard for Verilog Hardware Description Language:

• 1364-2005.

• 1364-2001.

• 1364-1995.

SystemVerilog

A unified hardware design, specification and verification language, standardized as IEEE Std. 1800 (see LRM). It extends Verilog by verification features like assertions, constrained random stimulus, functional coverage and object-oriented testbenches. Since IEEE Std. 1800-2009, SystemVerilog includes Verilog.

pySVModel names the language revisions in SystemVerilogVersion.

Wikipedia: https://en.wikipedia.org/wiki/SystemVerilog

Verilog

A hardware description language, standardized as IEEE Std. 1364 in 1995, 2001 and 2005 (see LRM). IEEE Std. 1800-2009 merged it into SystemVerilog.

Wikipedia: https://en.wikipedia.org/wiki/Verilog