Coverage for pySVModel/__init_

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31"""

32An abstract SystemVerilog language model.

34This package provides a unified abstract language model for SystemVerilog. Projects reading from source files can derive

35own classes and implement additional logic to create a concrete language model for their tools.

37Projects consuming pre-processed SystemVerilog data can build higher level features and services on such a model, while

38supporting multiple frontends.

40.. admonition:: Copyright Information

43 :license: Apache License, Version 2.0

44"""

45from enum import unique, Enum

46from typing import Dict, Union

48from pyTooling.Decorators import export

51__author__ = "Patrick Lehmann"

52__email__ = "Paebbels@gmail.com"

53__copyright__ = "2021-2024, Patrick Lehmann"

54__license__ = "Apache License, Version 2.0"

55__version__ = "0.5.1"

58@export

59@unique

60class SystemVerilogVersion(Enum):

61 """

62 An enumeration for all possible version numbers for (System)Verilog.

64 A version can be given as integer or string and is represented as a unified

65 enumeration value.

67 This enumeration supports compare operators.

68 """

69 Any = -1 #: Any

71 Verilog95 = 95 #: Verilog-1995

72 Verilog2001 = 1 #: Verilog-2001

73 Verilog2005 = 5 #: Verilog-2005

75 SystemVerilog2005 = 2005 #: SystemVerilog-2005

76 SystemVerilog2009 = 2009 #: SystemVerilog-2009

77 SystemVerilog2012 = 2012 #: SystemVerilog-2012

78 SystemVerilog2017 = 2017 #: SystemVerilog-2017

80 Latest = 10000 #: Latest Systemverilog (2017)

82 __VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {

83 -1: Any,

84 95: Verilog95,

85 1: Verilog2001,

86 5: Verilog2005,

87 # 5: SystemVerilog2005, # prefer Verilog on numbers below 2000

88 9: SystemVerilog2009,

89 12: SystemVerilog2012,

90 17: SystemVerilog2017,

91 1995: Verilog95,

92 2001: Verilog2001,

93 # 2005: Verilog2005, # prefer SystemVerilog on numbers above 2000

94 2005: SystemVerilog2005,

95 2009: SystemVerilog2009,

96 2012: SystemVerilog2012,

97 2017: SystemVerilog2017,

98 10000: Latest,

99 "Any": Any,

100 "95": Verilog95,

101 "01": Verilog2001,

102 "05": Verilog2005,

103 # "05": SystemVerilog2005, # prefer Verilog on numbers below 2000

104 "09": SystemVerilog2009,

105 "12": SystemVerilog2012,

106 "17": SystemVerilog2017,

107 "1995": Verilog95,

108 "2001": Verilog2001,

109 # "2005": Verilog2005, # prefer SystemVerilog on numbers above 2000

110 "2005": SystemVerilog2005,

111 "2009": SystemVerilog2009,

112 "2012": SystemVerilog2012,

113 "2017": SystemVerilog2017,

114 "Latest": Latest

115 } #: Dictionary of (System)Verilog year codes variants as integer and strings for mapping to unique enum values.

116

117 def __init__(self, *_):

118 """Patch the embedded MAP dictionary"""

119 for k, v in self.__class__.__VERSION_MAPPINGS__.items():

120 if (not isinstance(v, self.__class__)) and (v == self.value):

121 self.__class__.__VERSION_MAPPINGS__[k] = self

122

123 @classmethod

124 def Parse(cls, value: Union[int, str]) -> "SystemVerilogVersion":

125 """

126 Parses a (System)Verilog year code as integer or string to an enum value.

127

128 :param value: (System)Verilog year code.

129 :returns: Enumeration value.

130 :raises ValueError: If the year code is not recognized.

131 """

132 try:

133 return cls.__VERSION_MAPPINGS__[value]

134 except KeyError:

135 raise ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__))

136

137 def __lt__(self, other: Any) -> bool:

138 """

139 Compare two (System)Verilog versions if the version is less than the second operand.

140

141 :param other: Parameter to compare against.

142 :returns: True if version is less than the second operand.

143 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.

144 """

145 if isinstance(other, SystemVerilogVersion):

146 return self.value < other.value

147 else:

148 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.")

149

150 def __le__(self, other: Any) -> bool:

151 """

152 Compare two (System)Verilog versions if the version is less or equal than the second operand.

153

154 :param other: Parameter to compare against.

155 :returns: True if version is less or equal than the second operand.

156 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.

157 """

158 if isinstance(other, SystemVerilogVersion):

159 return self.value <= other.value

160 else:

161 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.")

162

163 def __gt__(self, other: Any) -> bool:

164 """

165 Compare two (System)Verilog versions if the version is greater than the second operand.

166

167 :param other: Parameter to compare against.

168 :returns: True if version is greater than the second operand.

169 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.

170 """

171 if isinstance(other, SystemVerilogVersion):

172 return self.value > other.value

173 else:

174 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.")

175

176 def __ge__(self, other: Any) -> bool:

177 """

178 Compare two (System)Verilog versions if the version is greater or equal than the second operand.

179

180 :param other: Parameter to compare against.

181 :returns: True if version is greater or equal than the second operand.

182 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.

183 """

184 if isinstance(other, SystemVerilogVersion):

185 return self.value >= other.value

186 else:

187 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.")

188

189 def __ne__(self, other: Any) -> bool:

190 """

191 Compare two (System)Verilog versions if the version is unequal to the second operand.

192

193 :param other: Parameter to compare against.

194 :returns: True if version is unequal to the second operand.

195 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.

196 """

197 if isinstance(other, SystemVerilogVersion):

198 return self.value != other.value

199 else:

200 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.")

201

202 def __eq__(self, other: Any) -> bool:

203 """

204 Compare two (System)Verilog versions if the version is equal to the second operand.

205

206 :param other: Parameter to compare against.

207 :returns: True if version is equal to the second operand.

208 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.

209 """

210 if isinstance(other, SystemVerilogVersion):

211 if (self is self.__class__.Any) or (other is self.__class__.Any):

212 return True

213 else:

214 return self.value == other.value

215 else:

216 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.")

217

218 @property

219 def IsVerilog(self) -> bool:

220 """

221 Checks if the version is a (classic) Verilog version.

222

223 :returns: True if version is a (classic) Verilog version.

224 """

225 return self in (self.Verilog95, self.Verilog2001, self.Verilog2005)

226

227 @property

228 def IsSystemVerilog(self) -> bool:

229 """

230 Checks if the version is a SystemVerilog version.

231

232 :returns: True if version is a SystemVerilog version.

233 """

234 return self in (self.SystemVerilog2005, self.SystemVerilog2009, self.SystemVerilog2012, self.SystemVerilog2017)

235

236 def __str__(self) -> str:

237 """

238 Formats the SystemVerilog version to pattern ``SV'xx`` or in case of classic Verilog to ``Verilog'xx``.

239

240 :return: Formatted (System)Verilog version.

241 """

242 if self.value == self.Any.value:

243 return "SV'Any"

244 if self.value == self.Latest.value: 244 ↛ 245line 244 didn't jump to line 245 because the condition on line 244 was never true

245 return "SV'Latest"

246

247 year = str(self.value)[-2:]

248 if self.value < self.SystemVerilog2005.value:

249 return f"Verilog'{year}"

250 else:

251 return f"SV'{year}"

252

253 def __repr__(self) -> str:

254 """

255 Formats the (System)Verilog version to pattern ``xxxx``.

256

257 :return: Formatted (System)Verilog version.

258 """

259 if self.value == self.Any.value:

260 return "Any"

261 elif self.value == self.Latest.value:

262 return "Latest"

263 else:

264 return str(self.value)

Coverage for pySVModel/init.py: 56%

78 statements