Coverage for pySVModel/__init__.py: 57%

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8# ==================================================================================================================== # 

9# Authors: # 

10# Patrick Lehmann # 

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13# ==================================================================================================================== # 

14# Copyright 2021-2026 Patrick Lehmann - Boetzingen, Germany # 

15# # 

16# Licensed under the Apache License, Version 2.0 (the "License"); # 

17# you may not use this file except in compliance with the License. # 

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30# 

31""" 

32An abstract SystemVerilog language model. 

33 

34This package provides a unified abstract language model for SystemVerilog. Projects reading from source files can derive 

35own classes and implement additional logic to create a concrete language model for their tools. 

36 

37Projects consuming pre-processed SystemVerilog data can build higher level features and services on such a model, while 

38supporting multiple frontends. 

39 

40.. admonition:: Copyright Information 

41 

42 :copyright: Copyright 2021-2026 Patrick Lehmann - Bötzingen, Germany 

43 :license: Apache License, Version 2.0 

44""" 

45from enum import unique, Enum 

46from typing import Dict, Union 

47 

48from pyTooling.Decorators import export 

49 

50 

51__author__ = "Patrick Lehmann" 

52__email__ = "Paebbels@gmail.com" 

53__copyright__ = "2021-2026, Patrick Lehmann" 

54__license__ = "Apache License, Version 2.0" 

55__version__ = "0.5.11" 

56# __keywords__ = [] 

57__project_url__ = "https://github.com/edaa-org/pySVModel" 

58__documentation_url__ = "https://edaa-org.github.io/pySVModel" 

59__issue_tracker_url__ = "https://GitHub.com/edaa-org/pySVModel/issues" 

60 

61 

62@export 

63@unique 

64class SystemVerilogVersion(Enum): 

65 """ 

66 An enumeration for all possible version numbers for (System)Verilog. 

67 

68 A version can be given as integer or string and is represented as a unified 

69 enumeration value. 

70 

71 This enumeration supports compare operators. 

72 """ 

73 Any = -1 #: Any 

74 

75 Verilog95 = 95 #: Verilog-1995 

76 Verilog2001 = 1 #: Verilog-2001 

77 Verilog2005 = 5 #: Verilog-2005 

78 

79 SystemVerilog2005 = 2005 #: SystemVerilog-2005 

80 SystemVerilog2009 = 2009 #: SystemVerilog-2009 

81 SystemVerilog2012 = 2012 #: SystemVerilog-2012 

82 SystemVerilog2017 = 2017 #: SystemVerilog-2017 

83 

84 Latest = 10000 #: Latest Systemverilog (2017) 

85 

86 __VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = { 

87 -1: Any, 

88 95: Verilog95, 

89 1: Verilog2001, 

90 5: Verilog2005, 

91 # 5: SystemVerilog2005, # prefer Verilog on numbers below 2000 

92 9: SystemVerilog2009, 

93 12: SystemVerilog2012, 

94 17: SystemVerilog2017, 

95 1995: Verilog95, 

96 2001: Verilog2001, 

97 # 2005: Verilog2005, # prefer SystemVerilog on numbers above 2000 

98 2005: SystemVerilog2005, 

99 2009: SystemVerilog2009, 

100 2012: SystemVerilog2012, 

101 2017: SystemVerilog2017, 

102 10000: Latest, 

103 "Any": Any, 

104 "95": Verilog95, 

105 "01": Verilog2001, 

106 "05": Verilog2005, 

107 # "05": SystemVerilog2005, # prefer Verilog on numbers below 2000 

108 "09": SystemVerilog2009, 

109 "12": SystemVerilog2012, 

110 "17": SystemVerilog2017, 

111 "1995": Verilog95, 

112 "2001": Verilog2001, 

113 # "2005": Verilog2005, # prefer SystemVerilog on numbers above 2000 

114 "2005": SystemVerilog2005, 

115 "2009": SystemVerilog2009, 

116 "2012": SystemVerilog2012, 

117 "2017": SystemVerilog2017, 

118 "Latest": Latest 

119 } #: Dictionary of (System)Verilog year codes variants as integer and strings for mapping to unique enum values. 

120 

121 def __init__(self, *_) -> None: 

122 """Patch the embedded MAP dictionary""" 

123 for k, v in self.__class__.__VERSION_MAPPINGS__.items(): 

124 if (not isinstance(v, self.__class__)) and (v == self.value): 

125 self.__class__.__VERSION_MAPPINGS__[k] = self 

126 

127 @classmethod 

128 def Parse(cls, value: Union[int, str]) -> "SystemVerilogVersion": 

129 """ 

130 Parses a (System)Verilog year code as integer or string to an enum value. 

131 

132 :param value: (System)Verilog year code. 

133 :returns: Enumeration value. 

134 :raises ValueError: If the year code is not recognized. 

135 """ 

136 try: 

137 return cls.__VERSION_MAPPINGS__[value] 

138 except KeyError: 

139 raise ValueError("Value '{0!s}' cannot be parsed to member of {1}.".format(value, cls.__name__)) 

140 

141 def __lt__(self, other: Any) -> bool: 

142 """ 

143 Compare two (System)Verilog versions if the version is less than the second operand. 

144 

145 :param other: Parameter to compare against. 

146 :returns: True if version is less than the second operand. 

147 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`. 

148 """ 

149 if isinstance(other, SystemVerilogVersion): 

150 return self.value < other.value 

151 else: 

152 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.") 

153 

154 def __le__(self, other: Any) -> bool: 

155 """ 

156 Compare two (System)Verilog versions if the version is less or equal than the second operand. 

157 

158 :param other: Parameter to compare against. 

159 :returns: True if version is less or equal than the second operand. 

160 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`. 

161 """ 

162 if isinstance(other, SystemVerilogVersion): 

163 return self.value <= other.value 

164 else: 

165 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.") 

166 

167 def __gt__(self, other: Any) -> bool: 

168 """ 

169 Compare two (System)Verilog versions if the version is greater than the second operand. 

170 

171 :param other: Parameter to compare against. 

172 :returns: True if version is greater than the second operand. 

173 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`. 

174 """ 

175 if isinstance(other, SystemVerilogVersion): 

176 return self.value > other.value 

177 else: 

178 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.") 

179 

180 def __ge__(self, other: Any) -> bool: 

181 """ 

182 Compare two (System)Verilog versions if the version is greater or equal than the second operand. 

183 

184 :param other: Parameter to compare against. 

185 :returns: True if version is greater or equal than the second operand. 

186 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`. 

187 """ 

188 if isinstance(other, SystemVerilogVersion): 

189 return self.value >= other.value 

190 else: 

191 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.") 

192 

193 def __ne__(self, other: Any) -> bool: 

194 """ 

195 Compare two (System)Verilog versions if the version is unequal to the second operand. 

196 

197 :param other: Parameter to compare against. 

198 :returns: True if version is unequal to the second operand. 

199 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`. 

200 """ 

201 if isinstance(other, SystemVerilogVersion): 

202 return self.value != other.value 

203 else: 

204 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.") 

205 

206 def __eq__(self, other: Any) -> bool: 

207 """ 

208 Compare two (System)Verilog versions if the version is equal to the second operand. 

209 

210 :param other: Parameter to compare against. 

211 :returns: True if version is equal to the second operand. 

212 :raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`. 

213 """ 

214 if isinstance(other, SystemVerilogVersion): 

215 if (self is self.__class__.Any) or (other is self.__class__.Any): 

216 return True 

217 else: 

218 return self.value == other.value 

219 else: 

220 raise TypeError("Second operand is not of type 'SystemVerilogVersion'.") 

221 

222 @property 

223 def IsVerilog(self) -> bool: 

224 """ 

225 Checks if the version is a (classic) Verilog version. 

226 

227 :returns: True if version is a (classic) Verilog version. 

228 """ 

229 return self in (self.Verilog95, self.Verilog2001, self.Verilog2005) 

230 

231 @property 

232 def IsSystemVerilog(self) -> bool: 

233 """ 

234 Checks if the version is a SystemVerilog version. 

235 

236 :returns: True if version is a SystemVerilog version. 

237 """ 

238 return self in (self.SystemVerilog2005, self.SystemVerilog2009, self.SystemVerilog2012, self.SystemVerilog2017) 

239 

240 def __str__(self) -> str: 

241 """ 

242 Formats the SystemVerilog version to pattern ``SV'xx`` or in case of classic Verilog to ``Verilog'xx``. 

243 

244 :returns: Formatted (System)Verilog version. 

245 """ 

246 if self.value == self.Any.value: 

247 return "SV'Any" 

248 if self.value == self.Latest.value: 248 ↛ 249line 248 didn't jump to line 249 because the condition on line 248 was never true

249 return "SV'Latest" 

250 

251 year = str(self.value)[-2:] 

252 if self.value < self.SystemVerilog2005.value: 

253 return f"Verilog'{year}" 

254 else: 

255 return f"SV'{year}" 

256 

257 def __repr__(self) -> str: 

258 """ 

259 Formats the (System)Verilog version to pattern ``xxxx``. 

260 

261 :returns: Formatted (System)Verilog version. 

262 """ 

263 if self.value == self.Any.value: 

264 return "Any" 

265 elif self.value == self.Latest.value: 

266 return "Latest" 

267 else: 

268 return str(self.value)