Code Coverage Report
| Package | Statments | Branches | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| Module | Total | Excluded | Covered | Missing | Coverage | Total | Covered | Partial | Missing | Coverage |
| 📦pyEDAA.ToolSetup | 0 | 0 | 0 | 0 | 0.0% | 0 | 0 | 0 | 0 | 0.0% |
| 📦ToolSetup | 157 | 9 | 118 | 39 | 75.2% | 22 | 2 | 2 | 20 | 18.2% |
| 📦Aldec | 24 | 0 | 22 | 2 | 91.7% | 0 | 0 | 0 | 0 | 0.0% |
| 📦IntelFPGA | 17 | 0 | 15 | 2 | 88.2% | 0 | 0 | 0 | 0 | 0.0% |
| 📦Lattice | 20 | 0 | 17 | 3 | 85.0% | 0 | 0 | 0 | 0 | 0.0% |
| 📦OpenSource | 16 | 0 | 14 | 2 | 87.5% | 0 | 0 | 0 | 0 | 0.0% |
| ⚙️GHDL | 51 | 9 | 35 | 16 | 68.6% | 2 | 0 | 0 | 2 | 0.0% |
| ⚙️GTKWave | 5 | 0 | 5 | 0 | 100.0% | 0 | 0 | 0 | 0 | 0.0% |
| 📦SiemensEDA | 19 | 0 | 17 | 2 | 89.5% | 0 | 0 | 0 | 0 | 0.0% |
| 📦SystemTools | 12 | 0 | 11 | 1 | 91.7% | 0 | 0 | 0 | 0 | 0.0% |
| 📦Xilinx | 30 | 0 | 26 | 4 | 86.7% | 0 | 0 | 0 | 0 | 0.0% |
| ⚙️DataModel | 120 | 7 | 110 | 10 | 91.7% | 0 | 0 | 0 | 0 | 0.0% |
| ⚙️Interface | 11 | 7 | 11 | 0 | 100.0% | 0 | 0 | 0 | 0 | 0.0% |
| Overall (13 files): | 482 | 32 | 401 | 81 | 83.2% | 24 | 2 | 2 | 22 | 16.7% |
| Code Coverage | Coverage Level |
|---|---|
| ≤10 % | almost unused |
| ≤20 % | almost unused |
| ≤30 % | almost unused |
| ≤40 % | poorly used |
| ≤50 % | poorly used |
| ≤60 % | somehow used |
| ≤70 % | somehow used |
| ≤80 % | somehow used |
| ≤85 % | well used |
| ≤90 % | well used |
| ≤95 % | well used |
| ≤100 % | excellently used |
Code coverage report generated with pytest, Coverage.py and visualized by sphinx-reports.