pySVModel

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pySVModel/__init__.pydocumentedundocumentedignoredexcludednot counted
31"""
32An abstract SystemVerilog language model.
33
34This package provides a unified abstract language model for SystemVerilog. Projects reading from source files can derive
35own classes and implement additional logic to create a concrete language model for their tools.
36
37Projects consuming pre-processed SystemVerilog data can build higher level features and services on such a model, while
38supporting multiple frontends.
39"""
...
44
46__author__ =            "Patrick Lehmann"
47__email__ =             "Paebbels@gmail.com"
48__copyright__ =         "2021-2026, Electronic Design Automation Abstraction (EDA²)"
49__license__ =           "Apache License, Version 2.0"
50__version__ =           "0.6.0"
52__project_url__ =       "https://github.com/edaa-org/pySVModel"
53__documentation_url__ = "https://edaa-org.github.io/pySVModel"
54__issue_tracker_url__ = "https://GitHub.com/edaa-org/pySVModel/issues"
55
57@export
58@unique
59class SystemVerilogVersion(Enum):
60	"""
61	An enumeration for all possible version numbers for (System)Verilog.
62
63	A version can be given as integer or string and is represented as a unified
64	enumeration value.
65
66	This enumeration supports compare operators.
67	"""
68	Any =                  -1  #: Any
69
70	Verilog95 =            95  #: Verilog-1995
71	Verilog2001 =           1  #: Verilog-2001
72	Verilog2005 =           5  #: Verilog-2005
73
74	SystemVerilog2005 =  2005  #: SystemVerilog-2005
75	SystemVerilog2009 =  2009  #: SystemVerilog-2009
76	SystemVerilog2012 =  2012  #: SystemVerilog-2012
77	SystemVerilog2017 =  2017  #: SystemVerilog-2017
78
79	Latest =            10000  #: Latest Systemverilog (2017)
80
81	__VERSION_MAPPINGS__: Dict[Union[int, str], Enum] = {
82		-1:       Any,
83		95:       Verilog95,
84		1:        Verilog2001,
85		5:        Verilog2005,
86		# 5:        SystemVerilog2005,    # prefer Verilog on numbers below 2000
87		9:        SystemVerilog2009,
88		12:       SystemVerilog2012,
89		17:       SystemVerilog2017,
90		1995:     Verilog95,
91		2001:     Verilog2001,
92		# 2005:     Verilog2005,          # prefer SystemVerilog on numbers above 2000
93		2005:     SystemVerilog2005,
94		2009:     SystemVerilog2009,
95		2012:     SystemVerilog2012,
96		2017:     SystemVerilog2017,
97		10000:    Latest,
98		"Any":    Any,
99		"95":     Verilog95,
100		"01":     Verilog2001,
101		"05":     Verilog2005,
102		# "05":     SystemVerilog2005,    # prefer Verilog on numbers below 2000
103		"09":     SystemVerilog2009,
104		"12":     SystemVerilog2012,
105		"17":     SystemVerilog2017,
106		"1995":   Verilog95,
107		"2001":   Verilog2001,
108		# "2005":   Verilog2005,          # prefer SystemVerilog on numbers above 2000
109		"2005":   SystemVerilog2005,
110		"2009":   SystemVerilog2009,
111		"2012":   SystemVerilog2012,
112		"2017":   SystemVerilog2017,
113		"Latest": Latest
114	}  #: Dictionary of (System)Verilog year codes variants as integer and strings for mapping to unique enum values.
115
116	def __init__(self, *_) -> None:
117		"""Patch the embedded MAP dictionary"""
		...
121
122	@classmethod
123	def Parse(cls, value: Union[int, str]) -> "SystemVerilogVersion":
124		"""
125		Parses a (System)Verilog year code as integer or string to an enum value.
126
127		:param value:       (System)Verilog year code.
128		:returns:           Enumeration value.
129		:raises ValueError: If the year code is not recognized.
130		"""
		...
135
136	def __lt__(self, other: Any) -> bool:
137		"""
138		Compare two (System)Verilog versions if the version is less than the second operand.
139
140		:param other:      Parameter to compare against.
141		:returns:          True if version is less than the second operand.
142		:raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.
143		"""
		...
148
149	def __le__(self, other: Any) -> bool:
150		"""
151		Compare two (System)Verilog versions if the version is less or equal than the second operand.
152
153		:param other:      Parameter to compare against.
154		:returns:          True if version is less or equal than the second operand.
155		:raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.
156		"""
		...
161
162	def __gt__(self, other: Any) -> bool:
163		"""
164		Compare two (System)Verilog versions if the version is greater than the second operand.
165
166		:param other:      Parameter to compare against.
167		:returns:          True if version is greater than the second operand.
168		:raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.
169		"""
		...
174
175	def __ge__(self, other: Any) -> bool:
176		"""
177		Compare two (System)Verilog versions if the version is greater or equal than the second operand.
178
179		:param other:      Parameter to compare against.
180		:returns:          True if version is greater or equal than the second operand.
181		:raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.
182		"""
		...
187
188	def __ne__(self, other: Any) -> bool:
189		"""
190		Compare two (System)Verilog versions if the version is unequal to the second operand.
191
192		:param other:      Parameter to compare against.
193		:returns:          True if version is unequal to the second operand.
194		:raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.
195		"""
		...
200
201	def __eq__(self, other: Any) -> bool:
202		"""
203		Compare two (System)Verilog versions if the version is equal to the second operand.
204
205		:param other:      Parameter to compare against.
206		:returns:          True if version is equal to the second operand.
207		:raises TypeError: If parameter ``other`` is not of type :class:`SystemVerilogVersion`.
208		"""
		...
216
217	@property
218	def IsVerilog(self) -> bool:
219		"""
220		Checks if the version is a (classic) Verilog version.
221
222		:returns:          True if version is a (classic) Verilog version.
223		"""
		...
225
226	@property
227	def IsSystemVerilog(self) -> bool:
228		"""
229		Checks if the version is a SystemVerilog version.
230
231		:returns:          True if version is a SystemVerilog version.
232		"""
		...
234
235	def __str__(self) -> str:
236		"""
237		Formats the SystemVerilog version to pattern ``SV'xx`` or in case of classic Verilog to ``Verilog'xx``.
238
239		:returns: Formatted (System)Verilog version.
240		"""
		...
251
252	def __repr__(self) -> str:
253		"""
254		Formats the (System)Verilog version to pattern ``xxxx``.
255
256		:returns: Formatted (System)Verilog version.
257		"""
		...