References#

[R1]

OpenROAD. URL: https://theopenroadproject.org/.

[R2]

Vikram Adve, Chris Lattner, and LLVM Developer Group. LLVM Project, a collection of modular and reusable compiler and toolchain technologies. 2003. URL: https://www.llvm.org/.

[R3]

Tutu Ajayi, D. Blaauw, T.-B. Chan, CK Cheng, Vidya A. Chhabria, Daniel K. Choo, Matteo Coltella, Ronald Dreslinski, Mateus Fogaça, Seyedpedram Hashemi, Abeba Ibrahim, Andrew B. Kahng, Meesun Kim, Jie Li, Zhengli Liang, Uday Mallappa, Peter Penzes, Geraldo Pradipta, S. Reda, Austin Rovinski, Kambiz Samadi, Sachin S. Sapatnekar, L. Saul, Carl Sechen, Vegi Srinivas, Wendy Swartz, Delyse Sylvester, Danny Urquhart, Ling-song Wang, Maverick Woo, and B. Xu. OpenROAD: Toward a Self-Driving, Open-Source Digital Layout Implementation Tool Chain. In Proc. Government Microcircuit Applications and Critical Technology Conference (GOMACTech). 2019. URL: https://par.nsf.gov/servlets/purl/10171024.

[R4]

Tim Ansell and Mehdi Saligane. The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : Invited Paper. In 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1–8. 2020. URL: https://dl.acm.org/doi/abs/10.1145/3400302.3415736.

[R5]

Lars Asplund, Olof Kraigher, and contributors. VUnit: a unit testing framework for VHDL/SystemVerilog. Sep 2014. URL: http://vunit.github.io.

[R6]

Lars Asplund and Unai Martinez-Corral. GitHub Facts About the HDL Industry. 2020. URL: https://larsasplund.github.io/github-facts.

[R7]

Georg Brandl, Takeshi KOMIYA, and contributors. Sphinx, Python Documentation Generator. 2007. URL: https://www.sphinx-doc.org.

[R8]

Tony Bybell and contributors. GTKWave: a is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX. 1998. URL: https://github.com/gtkwave/gtkwave.

[R9]

Aliaksei Chapyzhenka and contributors. Wavedrom, digital timing diagram rendering engine. 2014. URL: https://github.com/wavedrom/wavedrom.

[R10]

Alain Dargelas and Henner Zeller. Universal Hardware Data Model. In Workshop on Open-Source EDA Technology 2020 (WOSET). 10 2020. URL: https://woset-workshop.github.io/PDFs/2020/a10.pdf.

[R11]

Alain Dargelas, Henner Zeller, and contributors. Surelog, SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. 2019. URL: https://github.com/alainmarcel/Surelog/.

[R12]

David Fang, Henner Zeller, and contributors. Verible, a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter. 2019. URL: https://chipsalliance.github.io/verible/.

[R13]

gatecat and contributors. nextpnr: portable FPGA place and route tool. URL: https://github.com/YosysHQ/nextpnr.

[R14]

Tristan Gingold and contributors. GHDL: open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL. Sep 2003. URL: https://github.com/ghdl/ghdl.

[R15]

Tristan Gingold and contributors. ghdl-yosys-plugin: VHDL synthesis (based on ghdl and yosys). 2017. URL: https://github.com/ghdl/ghdl-yosys-plugin.

[R16]

Chris Higgs, Stuart Hodgson, and contributors. Coroutine Cosimulation TestBench (cocotb). Jun 2013. URL: https://github.com/cocotb/cocotb.

[R17]

Andrew B. Kahng. Open-Source EDA: If We Build It, Who Will Come? In 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC), 1–6. 2020. doi:10.1109/VLSI-SOC46417.2020.9344073.

[R18]

Olof Kindgren and contributors. FuseSoC: package manager and build abstraction tool for FPGA/ASIC development. 2011. URL: https://github.com/olofk/fusesoc.

[R19]

Olof Kindgren and contributors. Edalize: an abstraction library for interfacing EDA tools. 2018. URL: https://github.com/olofk/edalize.

[R20]

Olof Kraigher and contributors. rust_hdl, a collection of HDL related tools. 2018. URL: https://github.com/kraigher/rust_hdl.

[R21]

Patrick Lehmann. A JSON library implemented in VHDL. Aug 2015. URL: https://github.com/Paebbels/JSON-for-VHDL.

[R22]

Patrick Lehmann. pyVHDLParser, a token-stream based parser for VHDL-2008. 2017. URL: https://github.com/Paebbels/pyVHDLParser.

[R23]

Patrick Lehmann. pyIPCMI: a Python-based IP Core Management Infrastructure. 2018. URL: https://github.com/Paebbels/pyIPCMI.

[R24]

Jim Lewis and contributors. OSVVM project simulation scripts. URL: https://github.com/OSVVM/OSVVM-Scripts.

[R25]

Jim Lewis and contributors. Open Source VHDL Verification Methodology (OSVVM). May 2013. URL: https://osvvm.org/.

[R26]

Unai Martinez-Corral and contributors. Open Source Verification Bundle (OSVB). March 2021. URL: https://umarcor.github.io/osvb.

[R27]

Rodrigo A. Melo. PyFPGA: a Python package to use FPGA development tools programmatically. 2019. URL: https://github.com/PyFPGA/pyfpga.

[R28]

Kamyar Mohajerani and contributors. Xeda: cross EDA Abstraction and Automation. 2020. URL: https://github.com/XedaHQ/xeda.

[R29]

Kevin E. Murray, Mohamed A. Elgammal, Vaughn Betz, Tim Ansell, Keith Rothman, and Alessandro Comodi. SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs. IEEE Micro, 40(4):49–57, 2020. doi:10.1109/MM.2020.2998435.

[R30]

Kevin E. Murray, Oleg Petelin, Sheng Zhong, Jia Min Wang, Mohamed Eldafrawy, Jean-Philippe Legault, Eugene Sha, Aaron G. Graham, Jean Wu, Matthew J. P. Walker, Hanqing Zeng, Panagiotis Patros, Jason Luu, Kenneth B. Kent, and Vaughn Betz. VTR 8: High-Performance CAD and Customizable FPGA Architecture Modelling. ACM Trans. Reconfigurable Technol. Syst., May 2020. URL: https://doi.org/10.1145/3388617, doi:10.1145/3388617.

[R31]

Austin Rovinski, Tutu Ajayi, Minsoo Kim, Guanru Wang, and Mehdi Saligane. Bridging Academic Open-Source EDA to Real-World Usability. In 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1–7. 2020. URL: https://dl.acm.org/doi/10.1145/3400302.3415734.

[R32]

Fabian Schuiki, Andreas Kurth, Tobias Grosser, and Luca Benini. LLHD: A Multi-Level Intermediate Representation for Hardware Description Languages. In Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2020, 258–271. New York, NY, USA, 2020. Association for Computing Machinery. URL: https://doi.org/10.1145/3385412.3386024, doi:10.1145/3385412.3386024.

[R33]

Wilson Snyder and contributors. Verilator, FOSS tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. 2003. URL: https://www.veripool.org/verilator/.

[R34]

Richard Stallman and contributors. GCC, the GNU Compiler Collection. May 1987. URL: http://gcc.gnu.org/.

[R35]

Richard Stallman and GNU Project. GDB: The GNU Project Debugger. 1986. URL: https://www.gnu.org/software/gdb/.

[R36]

Espen Tallaksen and contributors. Universal VHDL Verification Methodology (UVVM). Sep 2013. URL: https://uvvm.org/.

[R37]

Kevin Thibedeau. Symbolator, a component diagramming tool for VHDL and Verilog. URL: https://kevinpt.github.io/symbolator.

[R38]

Lukas Vik and contributors. tsfpga: a project platform for modern FPGA development. URL: https://gitlab.com/tsfpga/tsfpga.

[R39]

Stephen Williams and contributors. Icarus Verilog, a Verilog simulation and synthesis tool. URL: http://iverilog.icarus.com/.

[R40]

Claire Wolf and contributors. SymbiYosys: front-end for Yosys-based formal verification flows. URL: https://github.com/YosysHQ/SymbiYosys.

[R41]

Claire Wolf and contributors. Yosys Open SYnthesis Suite. URL: https://github.com/YosysHQ/yosys.

[R42]

Clifford Wolf and Johann Glaser. A Free Verilog Synthesis Suite. In Proceedings of Austrochip 2013. 2013. URL: https://yosyshq.net/yosys/.

[R43]

GitHub. GitHub Actions. 2019. URL: https://github.com/features/actions.

[R44]

GitLab. GitLab CI/CD. URL: https://docs.gitlab.com/ee/ci/.