Languages and Data¶
Language Models¶
VHDLModel¶
pyVHDLModel ➚ is an abstract syntax and semantic model of the Verification and Hardware Description Language (VHDL). Such a Code Document Object Model (Code DOM) is an strongly typed hierarchy of classes with lots of types cross-references. Every language element or feature is represented by an object instance. Thus, an instance of a syntax model is a in-memory representation of a VHDL code snippet or source file, as a network of manifoldly linked objects.
SVModel¶
pySVModel ➚ is an abstract syntax model of the SystemVerilog language.
Hint
This language model is currently a placeholder. Skilled contributors are welcome to implement a Code Document Object Model (Code DOM) similar to the pyVHDLModel, so (System)Verilog source files can be accessed as a network of Python class instances (see edaa-org/pySVModel#11).
Data Models¶
Reports¶
Todo
Needs a short description paragraph.
UCIS¶
Todo
Needs a short description paragraph.
IPXACT¶
Todo
Needs a short description paragraph.