ActiveHDL¶
Todo
Needs documentation.
VHDL Library Tool¶
Arguments¶
Todo
Extract the following table from source code by scanning for CLIArgument attributes.
vlib Option |
Argument Class |
Description |
|
|
Library name to create. |
Usage¶
vlib = VHDLLibraryTool()
vlib[vlib.ValueLibraryName] = "PoC"
print(vlib.AsArgument())
VHDL Compiler¶
Arguments¶
Todo
Extract the following table from source code by scanning for CLIArgument attributes.
vcom Option |
Argument Class |
Description |
Usage¶
vcom = VHDLCompiler()
# vcom[vcom.ValueLibraryName] = "PoC"
print(vcom.AsArgument())
(System-)Verilog Compiler¶
Todo
This tool is not yet wrapped in Python using CLIAbstraction.
Arguments¶
Todo
Extract the following table from source code by scanning for CLIArgument attributes.
vlog Option |
Argument Class |
Description |
Usage¶
vlog = VerilogCompiler()
# vlog[vlog.ValueLibraryName] = "PoC"
print(vlog.AsArgument())
VHDL Simulator¶
Arguments¶
Todo
Extract the following table from source code by scanning for CLIArgument attributes.
vsim Option |
Argument Class |
Description |
Usage¶
vsim = VHDLSimulator()
# vsim[vsim.ValueLibraryName] = "PoC"
print(vsim.AsArgument())