Code Coverage of pyEDAA.OutputFilter: 90%

Files Functions Classes

coverage.py v7.13.5, created at 2026-04-10 22:28 +0000

      Statements   Branches   Total
File class   coverage statements missing excluded   coverage branches partial   coverage
pyEDAA / OutputFilter / Xilinx / Commands.py Command   86% 29 4 0   79% 14 3   84%
pyEDAA / OutputFilter / Xilinx / Commands.py CommandWithSections   50% 4 2 0   100% 0 0   50%
pyEDAA / OutputFilter / Xilinx / Commands.py CommandWithTasks   50% 4 2 0   100% 0 0   50%
pyEDAA / OutputFilter / Xilinx / Commands.py SynthesizeDesign   67% 81 27 0   66% 44 5   66%
pyEDAA / OutputFilter / Xilinx / Commands.py LinkDesign   81% 62 12 0   81% 32 6   81%
pyEDAA / OutputFilter / Xilinx / Commands.py OptimizeDesign   85% 41 6 0   80% 20 4   84%
pyEDAA / OutputFilter / Xilinx / Commands.py PlaceDesign   83% 41 7 0   75% 20 5   80%
pyEDAA / OutputFilter / Xilinx / Commands.py PhysicalOptimizeDesign   85% 41 6 0   75% 20 5   82%
pyEDAA / OutputFilter / Xilinx / Commands.py RouteDesign   83% 41 7 0   75% 20 5   80%
pyEDAA / OutputFilter / Xilinx / Commands.py (no class)   100% 144 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / Common.py Line   75% 20 5 0   100% 2 0   77%
pyEDAA / OutputFilter / Xilinx / Common.py VivadoMessage   100% 11 0 0   100% 2 0   100%
pyEDAA / OutputFilter / Xilinx / Common.py VivadoInfoMessage   100% 1 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / Common.py VivadoIrregularInfoMessage   75% 4 1 0   100% 2 0   83%
pyEDAA / OutputFilter / Xilinx / Common.py VivadoWarningMessage   100% 1 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / Common.py VivadoIrregularWarningMessage   50% 4 2 0   50% 2 1   50%
pyEDAA / OutputFilter / Xilinx / Common.py VivadoCriticalWarningMessage   100% 1 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / Common.py VivadoErrorMessage   100% 1 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / Common.py VHDLReportMessage   86% 7 1 0   50% 2 1   78%
pyEDAA / OutputFilter / Xilinx / Common.py TclCommand   62% 8 3 0   100% 0 0   62%
pyEDAA / OutputFilter / Xilinx / Common.py VivadoTclCommand   83% 6 1 0   100% 0 0   83%
pyEDAA / OutputFilter / Xilinx / Common.py (no class)   100% 201 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / Common2.py UndetectedEnd   67% 3 1 0   100% 0 0   67%
pyEDAA / OutputFilter / Xilinx / Common2.py UnknownLine   0% 3 3 0   100% 0 0   0%
pyEDAA / OutputFilter / Xilinx / Common2.py VivadoMessagesMixin   90% 30 3 0   100% 12 0   93%
pyEDAA / OutputFilter / Xilinx / Common2.py BaseParser   100% 1 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / Common2.py Parser   67% 3 1 0   100% 0 0   67%
pyEDAA / OutputFilter / Xilinx / Common2.py Preamble   91% 23 2 0   88% 8 1   90%
pyEDAA / OutputFilter / Xilinx / Common2.py Task   89% 37 4 0   81% 16 3   87%
pyEDAA / OutputFilter / Xilinx / Common2.py TaskWithSubTasks   84% 37 6 0   78% 18 4   82%
pyEDAA / OutputFilter / Xilinx / Common2.py SubTask   89% 37 4 0   81% 16 3   87%
pyEDAA / OutputFilter / Xilinx / Common2.py TaskWithPhases   93% 42 3 0   90% 20 2   92%
pyEDAA / OutputFilter / Xilinx / Common2.py Phase   78% 45 10 0   59% 22 5   72%
pyEDAA / OutputFilter / Xilinx / Common2.py PhaseWithChildren   79% 43 9 0   83% 18 3   80%
pyEDAA / OutputFilter / Xilinx / Common2.py SubPhase   90% 40 4 0   75% 16 4   86%
pyEDAA / OutputFilter / Xilinx / Common2.py SubPhaseWithChildren   86% 37 5 0   81% 16 3   85%
pyEDAA / OutputFilter / Xilinx / Common2.py SubSubPhase   92% 40 3 0   79% 14 3   89%
pyEDAA / OutputFilter / Xilinx / Common2.py SubSubPhaseWithChildren   94% 33 2 0   75% 16 4   88%
pyEDAA / OutputFilter / Xilinx / Common2.py SubSubSubPhase   93% 42 3 0   79% 14 3   89%
pyEDAA / OutputFilter / Xilinx / Common2.py (no class)   100% 193 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / Exception.py ClassificationException   75% 4 1 0   100% 0 0   75%
pyEDAA / OutputFilter / Xilinx / Exception.py (no class)   100% 14 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / OptimizeDesign.py (no class)   100% 157 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / PhysicalOptimizeDesign.py (no class)   100% 32 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / PlaceDesign.py (no class)   100% 211 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / RouteDesign.py (no class)   100% 227 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py BaseSection   0% 3 3 0   100% 0 0   0%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py Section   77% 39 9 0   69% 16 5   75%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py SubSection   67% 36 12 0   43% 14 6   60%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py RTLElaboration   81% 26 5 0   83% 18 3   82%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py LoadingPart   75% 20 5 0   75% 8 2   75%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py RTLComponentStatistics   71% 14 4 0   67% 6 2   70%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py IOInsertion   85% 40 6 0   75% 20 5   82%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py WritingSynthesisReport   85% 75 11 0   70% 30 9   81%
pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py (no class)   100% 136 0 0   100% 0 0   100%
pyEDAA / OutputFilter / Xilinx / __init__.py Processor   95% 118 6 0   96% 54 2   95%
pyEDAA / OutputFilter / Xilinx / __init__.py Document   90% 10 1 0   100% 2 0   92%
pyEDAA / OutputFilter / Xilinx / __init__.py (no class)   100% 42 0 0   100% 0 0   100%
pyEDAA / OutputFilter / __init__.py (no class)   100% 13 0 0   100% 0 0   100%
Total     92% 2659 212 0   78% 554 107   90%

No items found using the specified filter.

155 empty classes skipped.