Code Coverage of pyEDAA.OutputFilter: 87%

Files Functions Classes

coverage.py v7.10.6, created at 2025-09-12 22:10 +0000

File class statements missing excluded branches partial coverage
pyEDAA/OutputFilter/Xilinx/Commands.py Command 28 3 0 14 3 86%
pyEDAA/OutputFilter/Xilinx/Commands.py CommandWithSections 4 2 0 0 0 50%
pyEDAA/OutputFilter/Xilinx/Commands.py CommandWithTasks 4 2 0 0 0 50%
pyEDAA/OutputFilter/Xilinx/Commands.py SynthesizeDesign 77 23 0 44 5 69%
pyEDAA/OutputFilter/Xilinx/Commands.py LinkDesign 62 12 0 32 6 81%
pyEDAA/OutputFilter/Xilinx/Commands.py OptimizeDesign 37 2 0 20 4 89%
pyEDAA/OutputFilter/Xilinx/Commands.py PlaceDesign 37 3 0 20 5 86%
pyEDAA/OutputFilter/Xilinx/Commands.py PhysicalOptimizeDesign 37 2 0 20 5 88%
pyEDAA/OutputFilter/Xilinx/Commands.py RouteDesign 37 3 0 20 5 86%
pyEDAA/OutputFilter/Xilinx/Commands.py (no class) 138 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/Common.py Line 20 6 0 2 0 73%
pyEDAA/OutputFilter/Xilinx/Common.py VivadoMessage 11 0 0 2 0 100%
pyEDAA/OutputFilter/Xilinx/Common.py VivadoInfoMessage 1 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/Common.py VivadoIrregularInfoMessage 4 4 0 2 0 0%
pyEDAA/OutputFilter/Xilinx/Common.py VivadoWarningMessage 1 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/Common.py VivadoIrregularWarningMessage 4 4 0 2 0 0%
pyEDAA/OutputFilter/Xilinx/Common.py VivadoCriticalWarningMessage 1 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/Common.py VivadoErrorMessage 1 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/Common.py VHDLReportMessage 7 1 0 2 1 78%
pyEDAA/OutputFilter/Xilinx/Common.py TclCommand 8 3 0 0 0 62%
pyEDAA/OutputFilter/Xilinx/Common.py VivadoTclCommand 6 1 0 0 0 83%
pyEDAA/OutputFilter/Xilinx/Common.py (no class) 201 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/Common2.py VivadoMessagesMixin 30 5 0 12 1 81%
pyEDAA/OutputFilter/Xilinx/Common2.py BaseParser 1 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/Common2.py Parser 3 1 0 0 0 67%
pyEDAA/OutputFilter/Xilinx/Common2.py Preamble 23 2 0 8 1 90%
pyEDAA/OutputFilter/Xilinx/Common2.py Task 40 11 0 16 6 70%
pyEDAA/OutputFilter/Xilinx/Common2.py Phase 33 3 0 16 4 86%
pyEDAA/OutputFilter/Xilinx/Common2.py SubPhase 33 2 0 16 3 90%
pyEDAA/OutputFilter/Xilinx/Common2.py SubSubPhase 31 2 0 14 3 89%
pyEDAA/OutputFilter/Xilinx/Common2.py SubSubSubPhase 31 2 0 14 3 89%
pyEDAA/OutputFilter/Xilinx/Common2.py (no class) 107 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/Exception.py ClassificationException 4 4 0 0 0 0%
pyEDAA/OutputFilter/Xilinx/Exception.py (no class) 14 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py Task 35 2 0 16 3 90%
pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py Phase 37 5 0 18 5 82%
pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py SubPhase 31 3 0 14 4 84%
pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py Phase1_Initialization 31 4 0 16 6 79%
pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py Phase2_TimerUpdateAndTimingDataCollection 31 4 0 16 6 79%
pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py Phase9_Finalization 31 4 0 16 6 79%
pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py LogicOptimizationTask 35 4 0 18 4 85%
pyEDAA/OutputFilter/Xilinx/OptimizeDesign.py (no class) 155 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/PhysicalOptimizeDesign.py PhysicalSynthesisTask 33 4 0 18 4 84%
pyEDAA/OutputFilter/Xilinx/PhysicalOptimizeDesign.py (no class) 32 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py Phase1_PlacerInitialization 31 2 0 16 4 87%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py Phase25_GlobalPlacePhase2 31 3 0 16 5 83%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py Phase2_GlobalPlacement 31 3 0 16 5 83%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py Phase3_DetailPlacement 31 4 0 16 6 79%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py Phase411_PostPlacementOptimization 32 2 0 16 4 88%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py Phase41_PostCommitOptimization 31 1 0 16 4 89%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py Phase43_PlacerReporting 31 3 0 16 5 83%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py Phase4_PostPlacementOptimizationAndCleanUp 28 2 0 14 4 86%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py PlacerTask 30 5 0 16 5 78%
pyEDAA/OutputFilter/Xilinx/PlaceDesign.py (no class) 206 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/RouteDesign.py Phase2_RouterInitialization 31 1 0 16 3 91%
pyEDAA/OutputFilter/Xilinx/RouteDesign.py Phase4_InitialRouting 31 4 0 16 6 79%
pyEDAA/OutputFilter/Xilinx/RouteDesign.py Phase5_RipUpAndReroute 31 3 0 16 5 83%
pyEDAA/OutputFilter/Xilinx/RouteDesign.py Phase6_DelayAndSkewOptimization 31 4 0 16 6 79%
pyEDAA/OutputFilter/Xilinx/RouteDesign.py Phase7_PostHoldFix 31 3 0 16 5 83%
pyEDAA/OutputFilter/Xilinx/RouteDesign.py RoutingTask 30 4 0 16 4 83%
pyEDAA/OutputFilter/Xilinx/RouteDesign.py (no class) 145 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py BaseSection 3 3 0 0 0 0%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py Section 39 9 0 16 5 75%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py SubSection 36 12 0 14 6 60%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py RTLElaboration 26 5 0 18 4 80%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py LoadingPart 20 7 0 8 2 61%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py RTLComponentStatistics 14 4 0 6 2 70%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py IOInsertion 40 6 0 20 5 82%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py WritingSynthesisReport 75 18 0 30 10 71%
pyEDAA/OutputFilter/Xilinx/SynthesizeDesign.py (no class) 132 0 0 0 0 100%
pyEDAA/OutputFilter/Xilinx/__init__.py Processor 118 14 0 54 9 87%
pyEDAA/OutputFilter/Xilinx/__init__.py Document 9 0 0 2 0 100%
pyEDAA/OutputFilter/Xilinx/__init__.py (no class) 40 0 0 0 0 100%
pyEDAA/OutputFilter/__init__.py (no class) 13 0 0 0 0 100%
Total   2904 255 0 814 207 87%

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100 empty classes skipped.