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| pyEDAA / OutputFilter / Xilinx / Common2.py |
SubPhase.__init__ |
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| pyEDAA / OutputFilter / Xilinx / Common2.py |
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| pyEDAA / OutputFilter / Xilinx / Common2.py |
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| pyEDAA / OutputFilter / Xilinx / Common2.py |
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| pyEDAA / OutputFilter / Xilinx / OptimizeDesign.py |
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157 |
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32 |
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0 |
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| pyEDAA / OutputFilter / Xilinx / PlaceDesign.py |
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211 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
Section.__init__ |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
Section._SectionStart |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
Section._SectionFinish |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
Section.Generator |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
SubSection.__init__ |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
SubSection._SectionStart |
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1 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
SubSection._SectionFinish |
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4 |
0 |
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50% |
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3 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
SubSection.Generator |
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50% |
14 |
7 |
0 |
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33% |
6 |
2 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
RTLElaboration.Generator |
|
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0 |
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3 |
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82% |
| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
LoadingPart.__init__ |
|
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
LoadingPart.Part |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
LoadingPart.Generator |
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76% |
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0 |
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75% |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
RTLComponentStatistics.Generator |
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4 |
0 |
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2 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
IOInsertion.__init__ |
|
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0 |
0 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
IOInsertion.Generator |
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84% |
38 |
6 |
0 |
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5 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
WritingSynthesisReport.__init__ |
|
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
WritingSynthesisReport.Cells |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
WritingSynthesisReport.Blackboxes |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
WritingSynthesisReport._BlackboxesGenerator |
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4 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
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4 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
WritingSynthesisReport.Generator |
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0 |
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1 |
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| pyEDAA / OutputFilter / Xilinx / SynthesizeDesign.py |
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136 |
0 |
0 |
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0 |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Processor.__init__ |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Processor.Commands |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Processor.Duration |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Processor.__getitem__ |
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100% |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Processor.IsIncompleteLog |
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0 |
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0 |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Processor.LineClassification |
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42 |
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0 |
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96% |
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1 |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Processor.CommandFinder |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Document.__init__ |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Document.Logfile |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
Document.Parse |
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| pyEDAA / OutputFilter / Xilinx / __init__.py |
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100% |
42 |
0 |
0 |
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100% |
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0 |
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100% |
| pyEDAA / OutputFilter / __init__.py |
(no function) |
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100% |
13 |
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0 |
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100% |
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0 |
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100% |