test_ImplementationLogFile
Summary
- Status:
✅ Passed
- Duration:
00:00:00.409
- Testsuite:
Standard Output
--------------------------------- Captured Log ---------------------------------
--------------------------------- Captured Out ---------------------------------
#x1B[90m#-----------------------------------------------------------#x1B[39m
#x1B[97m# Vivado v2025.1 (64-bit)#x1B[39m
#x1B[37m# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025#x1B[39m
#x1B[37m# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025#x1B[39m
#x1B[37m# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025#x1B[39m
#x1B[97m# Start of session at: Thu Jun 12 18:39:05 2025#x1B[39m
#x1B[37m# Process ID : 28856#x1B[39m
#x1B[37m# Current directory : C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1#x1B[39m
#x1B[37m# Command line : vivado.exe -log toplevel.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source toplevel.tcl -notrace#x1B[39m
#x1B[37m# Log file : C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1/toplevel.vdi#x1B[39m
#x1B[37m# Journal file : C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1\vivado.jou#x1B[39m
#x1B[37m# Running On : Paebbels#x1B[39m
#x1B[37m# Platform : Windows Server 2016 or Windows 10#x1B[39m
#x1B[37m# Operating System : 26100#x1B[39m
#x1B[37m# Processor Detail : 11th Gen Intel(R) Core(TM) i9-11950H @ 2.60GHz#x1B[39m
#x1B[37m# CPU Frequency : 2611 MHz#x1B[39m
#x1B[37m# CPU Physical cores : 8#x1B[39m
#x1B[37m# CPU Logical cores : 16#x1B[39m
#x1B[37m# Host memory : 34048 MB#x1B[39m
#x1B[37m# Swap memory : 28991 MB#x1B[39m
#x1B[37m# Total Virtual : 63039 MB#x1B[39m
#x1B[37m# Available Virtual : 29246 MB#x1B[39m
#x1B[90m#-----------------------------------------------------------#x1B[39m
#x1B[96msource toplevel.tcl -notrace#x1B[39m
#x1B[96mCommand: link_design -top toplevel -part xc7a100tcsg324-1#x1B[39m
#x1B[90mDesign is defaulting to srcset: sources_1#x1B[39m
#x1B[90mDesign is defaulting to constrset: constrs_1#x1B[39m
#x1B[34mLoading part xc7a100tcsg324-1#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 719.387 ; gain = 0.000#x1B[39m
#x1B[34mAnalyzing 12 Unisim elements for replacement#x1B[39m
#x1B[34mUnisim Transformation completed in 0 CPU seconds#x1B[39m
#x1B[34mNetlist was created with Vivado 2025.1#x1B[39m
#x1B[34mPreparing netlist for logic optimization#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/Clock.xdc]#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/Clock.xdc]#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/ClockNetwork.xdc]#x1B[39m
#x1B[34mDone setting XDC timing constraints. [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/ClockNetwork.xdc:2]#x1B[39m
#x1B[34mDeriving generated clocks [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/ClockNetwork.xdc:2]#x1B[39m
#x1B[90mcreate_generated_clock: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1413.680 ; gain = 570.484#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/ClockNetwork.xdc]#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/target.xdc]#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/target.xdc]#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/Reset.xdc]#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/Reset.xdc]#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/Button.xdc]#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/Button.xdc]#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/Display.xdc]#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/Display.xdc]#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc] for cell 'clkNet/syncLocked100MHz'#x1B[39m
#x1B[93mNo cells matched 'gen[*].Sync/FF2'. [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc:2]#x1B[39m
#x1B[95m'set_property' expects at least one object. [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc:2]#x1B[39m
#x1B[37mResolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc] for cell 'clkNet/syncLocked100MHz'#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc] for cell 'clkNet/syncControlClock'#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc] for cell 'clkNet/syncControlClock'#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc] for cell 'clkNet/syncLocked200MHz'#x1B[39m
#x1B[93mNo cells matched 'gen[*].Sync/FF2'. [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc:2]#x1B[39m
#x1B[95m'set_property' expects at least one object. [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc:2]#x1B[39m
#x1B[37mResolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc] for cell 'clkNet/syncLocked200MHz'#x1B[39m
#x1B[97mParsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc] for cell 'inputSync'#x1B[39m
#x1B[97mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/xdc/withTiming/sync_Bits_Xilinx.xdc] for cell 'inputSync'#x1B[39m
#x1B[34mPushed 0 inverter(s) to 0 load pin(s).#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1413.680 ; gain = 0.000#x1B[39m
#x1B[34mUnisim Transformation Summary:#x1B[39m
#x1B[90mNo Unisim elements were transformed.#x1B[39m
#x1B[39m#x1B[39m
#x1B[90m9 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.#x1B[39m
#x1B[92mlink_design completed successfully#x1B[39m
#x1B[32mlink_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1413.680 ; gain = 906.434#x1B[39m
#x1B[96mCommand: opt_design#x1B[39m
#x1B[90mAttempting to get a license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[34mGot license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[90mRunning DRC as a precondition to command opt_design#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting DRC Task#x1B[39m
#x1B[34mRunning DRC with 2 threads#x1B[39m
#x1B[34mDRC finished with 0 Errors#x1B[39m
#x1B[34mPlease refer to the DRC report (report_drc) for more information.#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1413.680 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Cache Timing Information Task#x1B[39m
#x1B[34mDone setting XDC timing constraints.#x1B[39m
#x1B[93mEnding Cache Timing Information Task | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1443.590 ; gain = 29.910#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Logic Optimization Task#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 1 Initialization#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 1.1 Core Generation And Design Setup#x1B[39m
#x1B[36mPhase 1.1 Core Generation And Design Setup | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 1.2 Setup Constraints And Sort Netlist#x1B[39m
#x1B[36mPhase 1.2 Setup Constraints And Sort Netlist | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[94mPhase 1 Initialization | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 2 Timer Update And Timing Data Collection#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.1 Timer Update#x1B[39m
#x1B[36mPhase 2.1 Timer Update | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.2 Timing Data Collection#x1B[39m
#x1B[36mPhase 2.2 Timing Data Collection | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[94mPhase 2 Timer Update And Timing Data Collection | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 3 Retarget#x1B[39m
#x1B[34mNumber of loadless carry chains removed were: 0#x1B[39m
#x1B[34mTotal Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0#x1B[39m
#x1B[34mPushed 0 inverter(s) to 0 load pin(s).#x1B[39m
#x1B[34mRetargeted 0 cell(s).#x1B[39m
#x1B[94mPhase 3 Retarget | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[37mRetarget | Checksum: 28fb88505#x1B[39m
#x1B[34mPhase Retarget created 0 cells and removed 0 cells#x1B[39m
#x1B[34mIn phase Retarget, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 4 Constant propagation#x1B[39m
#x1B[34mPushed 0 inverter(s) to 0 load pin(s).#x1B[39m
#x1B[94mPhase 4 Constant propagation | Checksum: 28fb88505#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[37mConstant propagation | Checksum: 28fb88505#x1B[39m
#x1B[34mPhase Constant propagation created 0 cells and removed 0 cells#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 5 Sweep#x1B[39m
#x1B[34mBuilding netlist checker database with flags, 0x8#x1B[39m
#x1B[90mDone building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[34mBuilding netlist checker database with flags, 0x8#x1B[39m
#x1B[90mDone building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[34mInstance clkNet/syncControlClock/gen[0].Sync/FF1_METASTABILITY_FFS with RLOC has been removed by Opt_design#x1B[39m
#x1B[34mInstance clkNet/syncLocked100MHz/gen[0].Sync/FF1_METASTABILITY_FFS with RLOC has been removed by Opt_design#x1B[39m
#x1B[34mInstance clkNet/syncLocked200MHz/gen[0].Sync/FF1_METASTABILITY_FFS with RLOC has been removed by Opt_design#x1B[39m
#x1B[94mPhase 5 Sweep | Checksum: 22ca0f51d#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[37mSweep | Checksum: 22ca0f51d#x1B[39m
#x1B[34mPhase Sweep created 0 cells and removed 12 cells#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 6 BUFG optimization#x1B[39m
#x1B[94mPhase 6 BUFG optimization | Checksum: 22ca0f51d#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[37mBUFG optimization | Checksum: 22ca0f51d#x1B[39m
#x1B[34mPhase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 7 Shift Register Optimization#x1B[39m
#x1B[34mSRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs#x1B[39m
#x1B[94mPhase 7 Shift Register Optimization | Checksum: 22ca0f51d#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[37mShift Register Optimization | Checksum: 22ca0f51d#x1B[39m
#x1B[34mPhase Shift Register Optimization created 0 cells and removed 0 cells#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 8 Post Processing Netlist#x1B[39m
#x1B[94mPhase 8 Post Processing Netlist | Checksum: 22ca0f51d#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[37mPost Processing Netlist | Checksum: 22ca0f51d#x1B[39m
#x1B[34mPhase Post Processing Netlist created 0 cells and removed 0 cells#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 9 Finalization#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 9.1 Finalizing Design Cores and Updating Shapes#x1B[39m
#x1B[36mPhase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 32cdc0057#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 9.2 Verifying Netlist Connectivity#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mStarting Connectivity Check Task#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[36mPhase 9.2 Verifying Netlist Connectivity | Checksum: 32cdc0057#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[94mPhase 9 Finalization | Checksum: 32cdc0057#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[90mOpt_design Change Summary#x1B[39m
#x1B[90m=========================#x1B[39m
#x1B[39m#x1B[39m
#x1B[39m#x1B[39m
#x1B[90m-------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[90m| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |#x1B[39m
#x1B[90m-------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[90m| Retarget | 0 | 0 | 2 |#x1B[39m
#x1B[90m| Constant propagation | 0 | 0 | 0 |#x1B[39m
#x1B[90m| Sweep | 0 | 12 | 0 |#x1B[39m
#x1B[90m| BUFG optimization | 0 | 0 | 0 |#x1B[39m
#x1B[90m| Shift Register Optimization | 0 | 0 | 0 |#x1B[39m
#x1B[90m| Post Processing Netlist | 0 | 0 | 0 |#x1B[39m
#x1B[90m-------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[39m#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mEnding Logic Optimization Task | Checksum: 32cdc0057#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Power Optimization Task#x1B[39m
#x1B[34mSkipping clock gating for clocks with a period < 2.00 ns.#x1B[39m
#x1B[93mEnding Power Optimization Task | Checksum: 32cdc0057#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Final Cleanup Task#x1B[39m
#x1B[93mEnding Final Cleanup Task | Checksum: 32cdc0057#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Netlist Obfuscation Task#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[93mEnding Netlist Obfuscation Task | Checksum: 32cdc0057#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[34mReleasing license: Implementation#x1B[39m
#x1B[90m34 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.#x1B[39m
#x1B[92mopt_design completed successfully#x1B[39m
#x1B[34mExecuting command : report_drc -file toplevel_drc_opted.rpt -pb toplevel_drc_opted.pb -rpx toplevel_drc_opted.rpx#x1B[39m
#x1B[96mCommand: report_drc -file toplevel_drc_opted.rpt -pb toplevel_drc_opted.pb -rpx toplevel_drc_opted.rpx#x1B[39m
#x1B[34mRefreshing IP repositories#x1B[39m
#x1B[34mNo user IP repositories specified#x1B[39m
#x1B[34mLoaded Vivado IP repository 'C:/Xilinx/2025.1/Vivado/data/ip'.#x1B[39m
#x1B[34mRunning DRC with 2 threads#x1B[39m
#x1B[34mThe results of DRC are in file C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1/toplevel_drc_opted.rpt.#x1B[39m
#x1B[92mreport_drc completed successfully#x1B[39m
#x1B[34mWriting timing data to binary archive.#x1B[39m
#x1B[90mWrite ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[90mWrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[90mWrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[90mWriting XDEF routing.#x1B[39m
#x1B[90mWriting XDEF routing logical nets.#x1B[39m
#x1B[90mWriting XDEF routing special nets.#x1B[39m
#x1B[90mWrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[90mWrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[90mWrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[90mWrite Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[34mThe checkpoint 'C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1/toplevel_opt.dcp' has been generated.#x1B[39m
#x1B[96mCommand: place_design#x1B[39m
#x1B[90mAttempting to get a license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[34mGot license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[34mReleasing license: Implementation#x1B[39m
#x1B[34mRunning DRC with 2 threads#x1B[39m
#x1B[34mDRC finished with 0 Errors#x1B[39m
#x1B[34mPlease refer to the DRC report (report_drc) for more information.#x1B[39m
#x1B[90mRunning DRC as a precondition to command place_design#x1B[39m
#x1B[34mRunning DRC with 2 threads#x1B[39m
#x1B[34mDRC finished with 0 Errors#x1B[39m
#x1B[34mPlease refer to the DRC report (report_drc) for more information.#x1B[39m
#x1B[34mMultithreading enabled for place_design using a maximum of 2 CPUs#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Placer Task#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 1 Placer Initialization#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 1.1 Placer Initialization Netlist Sorting#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[36mPhase 1.1 Placer Initialization Netlist Sorting | Checksum: 293a287be#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 1.2 IO Placement/ Clock Placement/ Build Placer Device#x1B[39m
#x1B[34mDone setting XDC timing constraints.#x1B[39m
#x1B[36mPhase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10e7928eb#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.144 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 1.3 Build Placer Netlist Model#x1B[39m
#x1B[36mPhase 1.3 Build Placer Netlist Model | Checksum: 1417b7f74#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.292 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 1.4 Constrain Clocks/Macros#x1B[39m
#x1B[36mPhase 1.4 Constrain Clocks/Macros | Checksum: 1417b7f74#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.297 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[94mPhase 1 Placer Initialization | Checksum: 1417b7f74#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.303 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 2 Global Placement#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.1 Floorplanning#x1B[39m
#x1B[36mPhase 2.1 Floorplanning | Checksum: 1cc8b6e3e#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.333 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.2 Update Timing before SLR Path Opt#x1B[39m
#x1B[36mPhase 2.2 Update Timing before SLR Path Opt | Checksum: 1ded722bc#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.348 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.3 Post-Processing in Floorplanning#x1B[39m
#x1B[36mPhase 2.3 Post-Processing in Floorplanning | Checksum: 18da95687#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.350 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.4 Global Place Phase1#x1B[39m
#x1B[36mPhase 2.4 Global Place Phase1 | Checksum: 191806171#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.559 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.5 Global Place Phase2#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.5.1 UpdateTiming Before Physical Synthesis#x1B[39m
#x1B[36mPhase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: 165bf5975#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.584 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.5.2 Physical Synthesis In Placer#x1B[39m
#x1B[34mFound 0 LUTNM shape to break, 2 LUT instances to create LUTNM shape#x1B[39m
#x1B[34mBreak lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0#x1B[39m
#x1B[34mEnd 1 Pass. Optimized 1 net or LUT. Breaked 0 LUT, combined 1 existing LUT and moved 0 existing LUT#x1B[39m
#x1B[34mNo nets found for high-fanout optimization.#x1B[39m
#x1B[34mOptimized 0 net. Created 0 new instance.#x1B[39m
#x1B[34mEnd 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[34mNo candidate cells for DSP register optimization found in the design.#x1B[39m
#x1B[34mEnd 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[34mNo candidate cells found for Shift Register to Pipeline optimization#x1B[39m
#x1B[34mEnd 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[34mNo candidate cells found for Shift Register optimization.#x1B[39m
#x1B[34mNo candidate cells for Shift Register optimization found in the design#x1B[39m
#x1B[34mEnd 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[34mNo candidate cells for BRAM register optimization found in the design#x1B[39m
#x1B[34mEnd 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[34mNo candidate cells for URAM register optimization found in the design#x1B[39m
#x1B[34mEnd 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[34mNo candidate cells for URAM register optimization found in the design#x1B[39m
#x1B[34mEnd 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[34mNo candidate nets found for dynamic/static region interface net replication#x1B[39m
#x1B[34mEnd 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mSummary of Physical Synthesis Optimizations#x1B[39m
#x1B[90m============================================#x1B[39m
#x1B[39m#x1B[39m
#x1B[39m#x1B[39m
#x1B[90m-----------------------------------------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[90m| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |#x1B[39m
#x1B[90m-----------------------------------------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[90m| LUT Combining | 0 | 1 | 1 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| Total | 0 | 1 | 1 | 0 | 9 | 00:00:00 |#x1B[39m
#x1B[90m-----------------------------------------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[39m#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.5.2 Physical Synthesis In Placer | Checksum: 198c28174#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.670 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[36mPhase 2.5 Global Place Phase2 | Checksum: 20eb9eccb#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.740 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[94mPhase 2 Global Placement | Checksum: 20eb9eccb#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.744 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 3 Detail Placement#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.1 Commit Multi Column Macros#x1B[39m
#x1B[36mPhase 3.1 Commit Multi Column Macros | Checksum: 162713c39#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.762 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.2 Commit Most Macros & LUTRAMs#x1B[39m
#x1B[36mPhase 3.2 Commit Most Macros & LUTRAMs | Checksum: 132f410ed#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.804 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.3 Area Swap Optimization#x1B[39m
#x1B[36mPhase 3.3 Area Swap Optimization | Checksum: 1cb671e23#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.810 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.4 Pipeline Register Optimization#x1B[39m
#x1B[36mPhase 3.4 Pipeline Register Optimization | Checksum: 10d1631d5#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.811 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.5 Fast Optimization#x1B[39m
#x1B[36mPhase 3.5 Fast Optimization | Checksum: 1a522bd0e#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.874 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.6 Small Shape Detail Placement#x1B[39m
#x1B[36mPhase 3.6 Small Shape Detail Placement | Checksum: 25f04285d#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.983 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.7 Re-assign LUT pins#x1B[39m
#x1B[36mPhase 3.7 Re-assign LUT pins | Checksum: 29985e407#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.989 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.8 Pipeline Register Optimization#x1B[39m
#x1B[36mPhase 3.8 Pipeline Register Optimization | Checksum: 1d212c799#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:00.990 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 3.9 Fast Optimization#x1B[39m
#x1B[36mPhase 3.9 Fast Optimization | Checksum: 1a0cbd762#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[94mPhase 3 Detail Placement | Checksum: 1a0cbd762#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1865.148 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 4 Post Placement Optimization and Clean-Up#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.1 Post Commit Optimization#x1B[39m
#x1B[34mDone setting XDC timing constraints.#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.1.1 Post Placement Optimization#x1B[39m
#x1B[90mPost Placement Optimization Initialization | Checksum: 1a8cbaaf2#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.1.1.1 BUFG Insertion#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mStarting Physical Synthesis Task#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 1 Physical Synthesis Initialization#x1B[39m
#x1B[34mMultithreading enabled for phys_opt_design using a maximum of 2 CPUs#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=-0.733 | TNS=-0.936 |#x1B[39m
#x1B[36mPhase 1 Physical Synthesis Initialization | Checksum: 1818afcc0#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1865.645 ; gain = 0.000#x1B[39m
#x1B[34mBUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.#x1B[39m
#x1B[36mEnding Physical Synthesis Task | Checksum: 22839c186#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 1865.645 ; gain = 0.000#x1B[39m
#x1B[90mPhase 4.1.1.1 BUFG Insertion | Checksum: 1a8cbaaf2#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.1.1.2 Post Placement Timing Optimization#x1B[39m
#x1B[34mPost Placement Timing Summary WNS=-0.733. For the most accurate timing information please run report_timing.#x1B[39m
#x1B[36mPhase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1ab6d66f4#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[36mPhase 4.1 Post Commit Optimization | Checksum: 1ab6d66f4#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.2 Post Placement Cleanup#x1B[39m
#x1B[36mPhase 4.2 Post Placement Cleanup | Checksum: 1ab6d66f4#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.3 Placer Reporting#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.3.1 Print Estimated Congestion#x1B[39m
#x1B[34mPost-Placement Estimated Congestion#x1B[39m
#x1B[90m ____________________________________________________#x1B[39m
#x1B[90m| | Global Congestion | Short Congestion |#x1B[39m
#x1B[90m| Direction | Region Size | Region Size |#x1B[39m
#x1B[90m|___________|___________________|___________________|#x1B[39m
#x1B[90m| North| 1x1| 1x1|#x1B[39m
#x1B[90m|___________|___________________|___________________|#x1B[39m
#x1B[90m| South| 1x1| 1x1|#x1B[39m
#x1B[90m|___________|___________________|___________________|#x1B[39m
#x1B[90m| East| 1x1| 1x1|#x1B[39m
#x1B[90m|___________|___________________|___________________|#x1B[39m
#x1B[90m| West| 1x1| 1x1|#x1B[39m
#x1B[90m|___________|___________________|___________________|#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.3.1 Print Estimated Congestion | Checksum: 1ab6d66f4#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[36mPhase 4.3 Placer Reporting | Checksum: 1ab6d66f4#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.4 Final Placement Cleanup#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.645 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[94mPhase 4 Post Placement Optimization and Clean-Up | Checksum: 1052dc01e#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[93mEnding Placer Task | Checksum: e8c0a217#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1865.645 ; gain = 0.496#x1B[39m
#x1B[90m79 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.#x1B[39m
#x1B[92mplace_design completed successfully#x1B[39m
#x1B[34mRunning report commands "report_control_sets, report_io, report_utilization" in parallel.#x1B[39m
#x1B[90mRunning report generation with 2 threads.#x1B[39m
#x1B[34mExecuting command : report_utilization -file toplevel_utilization_placed.rpt -pb toplevel_utilization_placed.pb#x1B[39m
#x1B[34mExecuting command : report_control_sets -verbose -file toplevel_control_sets_placed.rpt#x1B[39m
#x1B[90mreport_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1865.645 ; gain = 0.000#x1B[39m
#x1B[34mExecuting command : report_io -file toplevel_io_placed.rpt#x1B[39m
#x1B[90mreport_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1865.645 ; gain = 0.000#x1B[39m
#x1B[34mWriting timing data to binary archive.#x1B[39m
#x1B[90mWrite ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1865.832 ; gain = 0.000#x1B[39m
#x1B[90mWrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1865.832 ; gain = 0.000#x1B[39m
#x1B[90mWrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1865.832 ; gain = 0.000#x1B[39m
#x1B[90mWriting XDEF routing.#x1B[39m
#x1B[90mWriting XDEF routing logical nets.#x1B[39m
#x1B[90mWriting XDEF routing special nets.#x1B[39m
#x1B[90mWrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1865.832 ; gain = 0.000#x1B[39m
#x1B[90mWrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1865.832 ; gain = 0.000#x1B[39m
#x1B[90mWrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1865.832 ; gain = 0.000#x1B[39m
#x1B[90mWrite Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1865.832 ; gain = 0.000#x1B[39m
#x1B[34mThe checkpoint 'C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1/toplevel_placed.dcp' has been generated.#x1B[39m
#x1B[96mCommand: phys_opt_design#x1B[39m
#x1B[90mAttempting to get a license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[34mGot license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Initial Update Timing Task#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1876.270 ; gain = 10.438#x1B[39m
#x1B[34mPhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 0.00s | WALL: 0.04s#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1876.270 ; gain = 0.000#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Physical Synthesis Task#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 1 Physical Synthesis Initialization#x1B[39m
#x1B[34mMultithreading enabled for phys_opt_design using a maximum of 2 CPUs#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=-0.733 | TNS=-0.936 |#x1B[39m
#x1B[94mPhase 1 Physical Synthesis Initialization | Checksum: 1d7156ac1#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.099 . Memory (MB): peak = 1876.289 ; gain = 0.020#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=-0.733 | TNS=-0.936 |#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 2 DSP Register Optimization#x1B[39m
#x1B[34mNo candidate cells for DSP register optimization found in the design.#x1B[39m
#x1B[34mEnd 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell#x1B[39m
#x1B[94mPhase 2 DSP Register Optimization | Checksum: 1d7156ac1#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.105 . Memory (MB): peak = 1876.289 ; gain = 0.020#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 3 Critical Path Optimization#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=-0.733 | TNS=-0.936 |#x1B[39m
#x1B[34mProcessed net NexysA7_GPIO_Seg7_Cathode_n_OBUF[1]. Re-placed instance NexysA7_GPIO_Seg7_Cathode_n_reg[1]#x1B[39m
#x1B[34mProcessed net NexysA7_GPIO_Seg7_Cathode_n_OBUF[1]. Optimization improves timing on the net.#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=-0.172 | TNS=-0.203 |#x1B[39m
#x1B[34mProcessed net NexysA7_GPIO_Seg7_Cathode_n_OBUF[2]. Re-placed instance NexysA7_GPIO_Seg7_Cathode_n_reg[2]#x1B[39m
#x1B[34mProcessed net NexysA7_GPIO_Seg7_Cathode_n_OBUF[2]. Optimization improves timing on the net.#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=-0.032 | TNS=-0.032 |#x1B[39m
#x1B[34mProcessed net NexysA7_GPIO_Seg7_Cathode_n_OBUF[3]. Re-placed instance NexysA7_GPIO_Seg7_Cathode_n_reg[3]#x1B[39m
#x1B[34mProcessed net NexysA7_GPIO_Seg7_Cathode_n_OBUF[3]. Optimization improves timing on the net.#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=0.152 | TNS=0.000 |#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=0.152 | TNS=0.000 |#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1876.289 ; gain = 0.000#x1B[39m
#x1B[94mPhase 3 Critical Path Optimization | Checksum: 1d7156ac1#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1876.289 ; gain = 0.020#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 4 Critical Path Optimization#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=0.152 | TNS=0.000 |#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=0.152 | TNS=0.000 |#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1876.289 ; gain = 0.000#x1B[39m
#x1B[94mPhase 4 Critical Path Optimization | Checksum: 1d7156ac1#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.141 . Memory (MB): peak = 1876.289 ; gain = 0.020#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1876.289 ; gain = 0.000#x1B[39m
#x1B[34mPost Physical Optimization Timing Summary | WNS=0.152 | TNS=0.000 |#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mSummary of Physical Synthesis Optimizations#x1B[39m
#x1B[90m============================================#x1B[39m
#x1B[39m#x1B[39m
#x1B[39m#x1B[39m
#x1B[90m-------------------------------------------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[90m| Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |#x1B[39m
#x1B[90m-------------------------------------------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[90m| DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 |#x1B[39m
#x1B[90m| Critical Path | 0.885 | 0.936 | 0 | 0 | 3 | 0 | 2 | 00:00:00 |#x1B[39m
#x1B[90m| Total | 0.885 | 0.936 | 0 | 0 | 3 | 0 | 3 | 00:00:00 |#x1B[39m
#x1B[90m-------------------------------------------------------------------------------------------------------------------------------------------------------------#x1B[39m
#x1B[39m#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1876.289 ; gain = 0.000#x1B[39m
#x1B[93mEnding Physical Synthesis Task | Checksum: 23fdcb99a#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.146 . Memory (MB): peak = 1876.289 ; gain = 0.020#x1B[39m
#x1B[34mReleasing license: Implementation#x1B[39m
#x1B[90m107 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.#x1B[39m
#x1B[92mphys_opt_design completed successfully#x1B[39m
#x1B[34mWriting timing data to binary archive.#x1B[39m
#x1B[90mWrite ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1894.160 ; gain = 0.000#x1B[39m
#x1B[90mWrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1894.160 ; gain = 0.000#x1B[39m
#x1B[90mWrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.160 ; gain = 0.000#x1B[39m
#x1B[90mWriting XDEF routing.#x1B[39m
#x1B[90mWriting XDEF routing logical nets.#x1B[39m
#x1B[90mWriting XDEF routing special nets.#x1B[39m
#x1B[90mWrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1894.160 ; gain = 0.000#x1B[39m
#x1B[90mWrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1894.160 ; gain = 0.000#x1B[39m
#x1B[90mWrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1894.160 ; gain = 0.000#x1B[39m
#x1B[90mWrite Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1894.160 ; gain = 0.000#x1B[39m
#x1B[34mThe checkpoint 'C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1/toplevel_physopt.dcp' has been generated.#x1B[39m
#x1B[96mCommand: route_design#x1B[39m
#x1B[90mAttempting to get a license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[34mGot license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[39m#x1B[39m
#x1B[39m#x1B[39m
#x1B[93mStarting Routing Task#x1B[39m
#x1B[34mMultithreading enabled for route_design using a maximum of 2 CPUs#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 1 Build RT Design#x1B[39m
#x1B[90mChecksum: PlaceDB: 2e5337de ConstDB: 0 ShapeSum: c67da98d RouteDB: b1d25f96#x1B[39m
#x1B[90mPost Restoration Checksum: NetGraph: c18fa37 | NumContArr: 982c0565 | Constraints: c2a8fa9d | Timing: c2a8fa9d#x1B[39m
#x1B[94mPhase 1 Build RT Design | Checksum: 22996f4d6#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2007.367 ; gain = 113.184#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 2 Router Initialization#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.1 Fix Topology Constraints#x1B[39m
#x1B[36mPhase 2.1 Fix Topology Constraints | Checksum: 22996f4d6#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2007.367 ; gain = 113.184#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.2 Pre Route Cleanup#x1B[39m
#x1B[36mPhase 2.2 Pre Route Cleanup | Checksum: 22996f4d6#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2007.367 ; gain = 113.184#x1B[39m
#x1B[90m Number of Nodes with overlaps = 0#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.3 Update Timing#x1B[39m
#x1B[36mPhase 2.3 Update Timing | Checksum: 2738a40b4#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2046.875 ; gain = 152.691#x1B[39m
#x1B[34mIntermediate Timing Summary | WNS=0.151 | TNS=0.000 | WHS=-0.136 | THS=-1.592 |#x1B[39m
#x1B[39m#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 2.4 Soft Constraint Pins - Fast Budgeting#x1B[39m
#x1B[36mPhase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 2be983164#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:30 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mRouter Utilization Summary#x1B[39m
#x1B[90m Global Vertical Routing Utilization = 0 %#x1B[39m
#x1B[90m Global Horizontal Routing Utilization = 0 %#x1B[39m
#x1B[90m Routable Net Status*#x1B[39m
#x1B[90m *Does not include unroutable nets such as driverless and loadless.#x1B[39m
#x1B[90m Run report_route_status for detailed report.#x1B[39m
#x1B[90m Number of Failed Nets = 142#x1B[39m
#x1B[90m (Failed Nets is the sum of unrouted and partially routed nets)#x1B[39m
#x1B[90m Number of Unrouted Nets = 142#x1B[39m
#x1B[90m Number of Partially Routed Nets = 0#x1B[39m
#x1B[90m Number of Node Overlaps = 0#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 2 Router Initialization | Checksum: 2be983164#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 3 Global Routing#x1B[39m
#x1B[94mPhase 3 Global Routing | Checksum: 2be983164#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 4 Initial Routing#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 4.1 Initial Net Routing Pass#x1B[39m
#x1B[36mPhase 4.1 Initial Net Routing Pass | Checksum: 25758a989#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[94mPhase 4 Initial Routing | Checksum: 25758a989#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 5 Rip-up And Reroute#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 5.1 Global Iteration 0#x1B[39m
#x1B[90m Number of Nodes with overlaps = 3#x1B[39m
#x1B[90m Number of Nodes with overlaps = 1#x1B[39m
#x1B[90m Number of Nodes with overlaps = 1#x1B[39m
#x1B[90m Number of Nodes with overlaps = 0#x1B[39m
#x1B[34mIntermediate Timing Summary | WNS=0.177 | TNS=0.000 | WHS=N/A | THS=N/A |#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 5.1 Global Iteration 0 | Checksum: 1f3951488#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 5.2 Global Iteration 1#x1B[39m
#x1B[90m Number of Nodes with overlaps = 1#x1B[39m
#x1B[90m Number of Nodes with overlaps = 0#x1B[39m
#x1B[34mIntermediate Timing Summary | WNS=0.177 | TNS=0.000 | WHS=N/A | THS=N/A |#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 5.2 Global Iteration 1 | Checksum: 131bc1f71#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[94mPhase 5 Rip-up And Reroute | Checksum: 131bc1f71#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 6 Delay and Skew Optimization#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 6.1 Delay CleanUp#x1B[39m
#x1B[36mPhase 6.1 Delay CleanUp | Checksum: 131bc1f71#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 6.2 Clock Skew Optimization#x1B[39m
#x1B[36mPhase 6.2 Clock Skew Optimization | Checksum: 131bc1f71#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[94mPhase 6 Delay and Skew Optimization | Checksum: 131bc1f71#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 7 Post Hold Fix#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 7.1 Hold Fix Iter#x1B[39m
#x1B[34mIntermediate Timing Summary | WNS=0.177 | TNS=0.000 | WHS=0.115 | THS=0.000 |#x1B[39m
#x1B[39m#x1B[39m
#x1B[36mPhase 7.1 Hold Fix Iter | Checksum: 11d393179#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[94mPhase 7 Post Hold Fix | Checksum: 11d393179#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 8 Route finalize#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mRouter Utilization Summary#x1B[39m
#x1B[90m Global Vertical Routing Utilization = 0.0267659 %#x1B[39m
#x1B[90m Global Horizontal Routing Utilization = 0.0105144 %#x1B[39m
#x1B[90m Routable Net Status*#x1B[39m
#x1B[90m *Does not include unroutable nets such as driverless and loadless.#x1B[39m
#x1B[90m Run report_route_status for detailed report.#x1B[39m
#x1B[90m Number of Failed Nets = 0#x1B[39m
#x1B[90m (Failed Nets is the sum of unrouted and partially routed nets)#x1B[39m
#x1B[90m Number of Unrouted Nets = 0#x1B[39m
#x1B[90m Number of Partially Routed Nets = 0#x1B[39m
#x1B[90m Number of Node Overlaps = 0#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 8 Route finalize | Checksum: 11d393179#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 9 Verifying routed nets#x1B[39m
#x1B[39m#x1B[39m
#x1B[90m Verification completed successfully#x1B[39m
#x1B[94mPhase 9 Verifying routed nets | Checksum: 11d393179#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 10 Depositing Routes#x1B[39m
#x1B[94mPhase 10 Depositing Routes | Checksum: 1d6662f6a#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 11 Post Process Routing#x1B[39m
#x1B[94mPhase 11 Post Process Routing | Checksum: 1d6662f6a#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 12 Post Router Timing#x1B[39m
#x1B[34mEstimated Timing Summary | WNS=0.177 | TNS=0.000 | WHS=0.115 | THS=0.000 |#x1B[39m
#x1B[39m#x1B[39m
#x1B[34mThe final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.#x1B[39m
#x1B[94mPhase 12 Post Router Timing | Checksum: 1d6662f6a#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[90mTotal Elapsed time in route_design: 28.284 secs#x1B[39m
#x1B[39m#x1B[39m
#x1B[94mPhase 13 Post-Route Event Processing#x1B[39m
#x1B[94mPhase 13 Post-Route Event Processing | Checksum: 1fcf54613#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[34mRouter Completed Successfully#x1B[39m
#x1B[93mEnding Routing Task | Checksum: 1fcf54613#x1B[39m
#x1B[39m#x1B[39m
#x1B[32mTime (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.770#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mRouting Is Done.#x1B[39m
#x1B[34mReleasing license: Implementation#x1B[39m
#x1B[90m119 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.#x1B[39m
#x1B[92mroute_design completed successfully#x1B[39m
#x1B[90mroute_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 2070.953 ; gain = 176.793#x1B[39m
#x1B[34mExecuting command : report_drc -file toplevel_drc_routed.rpt -pb toplevel_drc_routed.pb -rpx toplevel_drc_routed.rpx#x1B[39m
#x1B[96mCommand: report_drc -file toplevel_drc_routed.rpt -pb toplevel_drc_routed.pb -rpx toplevel_drc_routed.rpx#x1B[39m
#x1B[34mIP Catalog is up to date.#x1B[39m
#x1B[34mRunning DRC with 2 threads#x1B[39m
#x1B[34mThe results of DRC are in file C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1/toplevel_drc_routed.rpt.#x1B[39m
#x1B[92mreport_drc completed successfully#x1B[39m
#x1B[34mExecuting command : report_methodology -file toplevel_methodology_drc_routed.rpt -pb toplevel_methodology_drc_routed.pb -rpx toplevel_methodology_drc_routed.rpx#x1B[39m
#x1B[96mCommand: report_methodology -file toplevel_methodology_drc_routed.rpt -pb toplevel_methodology_drc_routed.pb -rpx toplevel_methodology_drc_routed.rpx#x1B[39m
#x1B[34mDone setting XDC timing constraints.#x1B[39m
#x1B[34mRunning Methodology with 2 threads#x1B[39m
#x1B[34mThe results of Report Methodology are in file C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1/toplevel_methodology_drc_routed.rpt.#x1B[39m
#x1B[92mreport_methodology completed successfully#x1B[39m
#x1B[34mExecuting command : report_timing_summary -max_paths 10 -report_unconstrained -file toplevel_timing_summary_routed.rpt -pb toplevel_timing_summary_routed.pb -rpx toplevel_timing_summary_routed.rpx -warn_on_violation#x1B[39m
#x1B[34mDone setting XDC timing constraints.#x1B[39m
#x1B[34mUpdateTimingParams: Speed grade: -1, Delay Type: min_max.#x1B[39m
#x1B[34mMultithreading enabled for timing update using a maximum of 2 CPUs#x1B[39m
#x1B[34mRunning report commands "report_incremental_reuse, report_route_status" in parallel.#x1B[39m
#x1B[90mRunning report generation with 2 threads.#x1B[39m
#x1B[34mExecuting command : report_incremental_reuse -file toplevel_incremental_reuse_routed.rpt#x1B[39m
#x1B[34mIncremental flow is disabled. No incremental reuse Info to report.#x1B[39m
#x1B[34mExecuting command : report_route_status -file toplevel_route_status.rpt -pb toplevel_route_status.pb#x1B[39m
#x1B[34mExecuting command : report_power -file toplevel_power_routed.rpt -pb toplevel_power_summary_routed.pb -rpx toplevel_power_routed.rpx#x1B[39m
#x1B[96mCommand: report_power -file toplevel_power_routed.rpt -pb toplevel_power_summary_routed.pb -rpx toplevel_power_routed.rpx#x1B[39m
#x1B[90mRunning Vector-less Activity Propagation...#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mFinished Running Vector-less Activity Propagation#x1B[39m
#x1B[90m136 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.#x1B[39m
#x1B[92mreport_power completed successfully#x1B[39m
#x1B[34mExecuting command : report_clock_utilization -file toplevel_clock_utilization_routed.rpt#x1B[39m
#x1B[34mExecuting command : report_bus_skew -warn_on_violation -file toplevel_bus_skew_routed.rpt -pb toplevel_bus_skew_routed.pb -rpx toplevel_bus_skew_routed.rpx#x1B[39m
#x1B[34mUpdateTimingParams: Speed grade: -1, Delay Type: min_max.#x1B[39m
#x1B[34mMultithreading enabled for timing update using a maximum of 2 CPUs#x1B[39m
#x1B[90mgenerate_parallel_reports: Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 2106.148 ; gain = 35.195#x1B[39m
#x1B[34mWriting timing data to binary archive.#x1B[39m
#x1B[90mWrite ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2106.148 ; gain = 0.000#x1B[39m
#x1B[90mWrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 2106.148 ; gain = 0.000#x1B[39m
#x1B[90mWrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.148 ; gain = 0.000#x1B[39m
#x1B[90mWriting XDEF routing.#x1B[39m
#x1B[90mWriting XDEF routing logical nets.#x1B[39m
#x1B[90mWriting XDEF routing special nets.#x1B[39m
#x1B[90mWrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2106.148 ; gain = 0.000#x1B[39m
#x1B[90mWrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.148 ; gain = 0.000#x1B[39m
#x1B[90mWrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2106.148 ; gain = 0.000#x1B[39m
#x1B[90mWrite Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2106.148 ; gain = 0.000#x1B[39m
#x1B[34mThe checkpoint 'C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/impl_1/toplevel_routed.dcp' has been generated.#x1B[39m
#x1B[96mCommand: write_bitstream -force toplevel.bit#x1B[39m
#x1B[90mAttempting to get a license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[34mGot license for feature 'Implementation' and/or device 'xc7a100t'#x1B[39m
#x1B[90mRunning DRC as a precondition to command write_bitstream#x1B[39m
#x1B[34mIP Catalog is up to date.#x1B[39m
#x1B[34mRunning DRC with 2 threads#x1B[39m
#x1B[34mDRC finished with 0 Errors#x1B[39m
#x1B[34mPlease refer to the DRC report (report_drc) for more information.#x1B[39m
#x1B[34mRunning write_bitstream with 2 threads.#x1B[39m
#x1B[90mLoading data files...#x1B[39m
#x1B[90mLoading site data...#x1B[39m
#x1B[90mLoading route data...#x1B[39m
#x1B[90mProcessing options...#x1B[39m
#x1B[90mCreating bitmap...#x1B[39m
#x1B[90mCreating bitstream...#x1B[39m
#x1B[90mWriting bitstream ./toplevel.bit...#x1B[39m
#x1B[34mBitgen Completed Successfully.#x1B[39m
#x1B[34mWebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.#x1B[39m
#x1B[34mReleasing license: Implementation#x1B[39m
#x1B[90m151 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.#x1B[39m
#x1B[92mwrite_bitstream completed successfully#x1B[39m
#x1B[32mwrite_bitstream: Time (s): cpu = 00:00:12 ; elapsed = 00:00:09 . Memory (MB): peak = 2610.207 ; gain = 504.059#x1B[39m
#x1B[34mExiting Vivado at Thu Jun 12 18:40:15 2025...#x1B[39m
Standard Error
--------------------------------- Captured Err ---------------------------------