test_SynthesisLogFile
Summary
- Status:
✅ Passed
- Duration:
00:00:00.238
- Testsuite:
Standard Output
--------------------------------- Captured Log ---------------------------------
--------------------------------- Captured Out ---------------------------------
#x1B[90m#-----------------------------------------------------------#x1B[39m
#x1B[97m# Vivado v2025.1 (64-bit)#x1B[39m
#x1B[37m# SW Build 6140274 on Thu May 22 00:12:29 MDT 2025#x1B[39m
#x1B[37m# IP Build 6138677 on Thu May 22 03:10:11 MDT 2025#x1B[39m
#x1B[37m# SharedData Build 6139179 on Tue May 20 17:58:58 MDT 2025#x1B[39m
#x1B[97m# Start of session at: Thu Jun 12 18:38:16 2025#x1B[39m
#x1B[37m# Process ID : 35836#x1B[39m
#x1B[37m# Current directory : C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/synth_1#x1B[39m
#x1B[37m# Command line : vivado.exe -log toplevel.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source toplevel.tcl#x1B[39m
#x1B[37m# Log file : C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/synth_1/toplevel.vds#x1B[39m
#x1B[37m# Journal file : C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/synth_1\vivado.jou#x1B[39m
#x1B[37m# Running On : Paebbels#x1B[39m
#x1B[37m# Platform : Windows Server 2016 or Windows 10#x1B[39m
#x1B[37m# Operating System : 26100#x1B[39m
#x1B[37m# Processor Detail : 11th Gen Intel(R) Core(TM) i9-11950H @ 2.60GHz#x1B[39m
#x1B[37m# CPU Frequency : 2611 MHz#x1B[39m
#x1B[37m# CPU Physical cores : 8#x1B[39m
#x1B[37m# CPU Logical cores : 16#x1B[39m
#x1B[37m# Host memory : 34048 MB#x1B[39m
#x1B[37m# Swap memory : 28991 MB#x1B[39m
#x1B[37m# Total Virtual : 63039 MB#x1B[39m
#x1B[37m# Available Virtual : 29171 MB#x1B[39m
#x1B[90m#-----------------------------------------------------------#x1B[39m
#x1B[96msource toplevel.tcl -notrace#x1B[39m
#x1B[96mCommand: synth_design -top toplevel -part xc7a100tcsg324-1 -assert -incremental_mode off#x1B[39m
#x1B[37mStarting synth_design#x1B[39m
#x1B[90mAttempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'#x1B[39m
#x1B[34mGot license for feature 'Synthesis' and/or device 'xc7a100t'#x1B[39m
#x1B[34mLoading part xc7a100tcsg324-1#x1B[39m
#x1B[34mMultithreading enabled for synth_design using a maximum of 2 processes.#x1B[39m
#x1B[34mLaunching helper process for spawning children vivado processes#x1B[39m
#x1B[34mHelper process launched with PID 24240#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStarting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1204.906 ; gain = 494.461#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[34msynthesizing module 'toplevel' [C:/Git/PLC2/Training/StopWatch/src/toplevel.WithTiming.vhdl:26]#x1B[39m
#x1B[34msynthesizing module 'ClockNetwork' [C:/Git/PLC2/Training/StopWatch/src/ClockNetwork.vhdl:33]#x1B[39m
#x1B[37m Parameter CLOCK_IN_FREQ bound to: 100000000.000000 - type: double#x1B[39m
#x1B[34msynthesizing module 'sync_Bits_Xilinx' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:101]#x1B[39m
#x1B[34msynthesizing module 'sync_Bit_Xilinx' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:119]#x1B[39m
#x1B[37m Parameter INIT bound to: 1'b0#x1B[39m
#x1B[37m Parameter SYNC_DEPTH bound to: 2 - type: integer#x1B[39m
#x1B[37m Parameter INIT bound to: 1'b0#x1B[39m
#x1B[34mbinding component instance 'FF1_METASTABILITY_FFS' to cell 'FD' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:144]#x1B[39m
#x1B[37m Parameter INIT bound to: 1'b0#x1B[39m
#x1B[34mbinding component instance 'FF2' to cell 'FD' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:154]#x1B[39m
#x1B[34mdone synthesizing module 'sync_Bit_Xilinx' (0#1) [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:119]#x1B[39m
#x1B[34mdone synthesizing module 'sync_Bits_Xilinx' (0#1) [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:101]#x1B[39m
#x1B[34mbinding component instance 'BUFR_Control_Clock' to cell 'BUFG' [C:/Git/PLC2/Training/StopWatch/src/ClockNetwork.vhdl:67]#x1B[39m
#x1B[34mbinding component instance 'BUFG_MMCM_Clock_100MHz' to cell 'BUFG' [C:/Git/PLC2/Training/StopWatch/src/ClockNetwork.vhdl:76]#x1B[39m
#x1B[34mbinding component instance 'BUFG_MMCM_Clock_200MHz' to cell 'BUFG' [C:/Git/PLC2/Training/StopWatch/src/ClockNetwork.vhdl:83]#x1B[39m
#x1B[37m Parameter BANDWIDTH bound to: LOW - type: string#x1B[39m
#x1B[37m Parameter CLKFBOUT_MULT_F bound to: 10.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKFBOUT_USE_FINE_PS bound to: 0 - type: bool#x1B[39m
#x1B[37m Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKIN2_PERIOD bound to: 10.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT0_USE_FINE_PS bound to: 0 - type: bool#x1B[39m
#x1B[37m Parameter CLKOUT1_DIVIDE bound to: 5 - type: integer#x1B[39m
#x1B[37m Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT1_PHASE bound to: 0.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT1_USE_FINE_PS bound to: 0 - type: bool#x1B[39m
#x1B[37m Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer#x1B[39m
#x1B[37m Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT2_USE_FINE_PS bound to: 0 - type: bool#x1B[39m
#x1B[37m Parameter CLKOUT3_DIVIDE bound to: 4 - type: integer#x1B[39m
#x1B[37m Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT3_USE_FINE_PS bound to: 0 - type: bool#x1B[39m
#x1B[37m Parameter CLKOUT4_CASCADE bound to: 0 - type: bool#x1B[39m
#x1B[37m Parameter CLKOUT4_DIVIDE bound to: 100 - type: integer#x1B[39m
#x1B[37m Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double#x1B[39m
#x1B[37m Parameter CLKOUT4_USE_FINE_PS bound to: 0 - type: bool#x1B[39m
#x1B[37m Parameter COMPENSATION bound to: BUF_IN - type: string#x1B[39m
#x1B[37m Parameter DIVCLK_DIVIDE bound to: 1 - type: integer#x1B[39m
#x1B[37m Parameter REF_JITTER1 bound to: 0.000480 - type: double#x1B[39m
#x1B[37m Parameter REF_JITTER2 bound to: 0.000480 - type: double#x1B[39m
#x1B[37m Parameter STARTUP_WAIT bound to: 0 - type: bool#x1B[39m
#x1B[34mbinding component instance 'System_MMCM' to cell 'MMCME2_ADV' [C:/Git/PLC2/Training/StopWatch/src/ClockNetwork.vhdl:92]#x1B[39m
#x1B[34mdone synthesizing module 'ClockNetwork' (0#1) [C:/Git/PLC2/Training/StopWatch/src/ClockNetwork.vhdl:33]#x1B[39m
#x1B[34msynthesizing module 'sync_Bits_Xilinx__parameterized0' [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:101]#x1B[39m
#x1B[37m Parameter BITS bound to: 2 - type: integer#x1B[39m
#x1B[34mdone synthesizing module 'sync_Bits_Xilinx__parameterized0' (0#1) [C:/Git/PLC2/Training/StopWatch/src/sync_Bits_Xilinx.vhdl:101]#x1B[39m
#x1B[34msynthesizing module 'Debouncer' [C:/Git/PLC2/Training/StopWatch/src/Debouncer.vhdl:23]#x1B[39m
#x1B[37m Parameter CLOCK_FREQ bound to: 64'b0000000000000000000000000000000000000101111101011110000100000000#x1B[39m
#x1B[37m Parameter BITS bound to: 2 - type: integer#x1B[39m
#x1B[34mRTL report: "TimingToCycles(time, freq): period=10.000000 ns -- 0.000000 fs" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:118]#x1B[39m
#x1B[34mRTL assertion: "CLOCK_FREQ: 100.000000 ns" [C:/Git/PLC2/Training/StopWatch/src/Debouncer.vhdl:28]#x1B[39m
#x1B[34mRTL assertion: "DEBOUNCE_TIME: 3.000000 ms" [C:/Git/PLC2/Training/StopWatch/src/Debouncer.vhdl:29]#x1B[39m
#x1B[34mRTL report: "TimingToCycles(time, freq): period=10.000000 ns -- 0.000000 fs" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:118]#x1B[39m
#x1B[34mdone synthesizing module 'Debouncer' (0#1) [C:/Git/PLC2/Training/StopWatch/src/Debouncer.vhdl:23]#x1B[39m
#x1B[34msynthesizing module 'Stopwatch' [C:/Git/PLC2/Training/StopWatch/src/StopWatch.vhdl:28]#x1B[39m
#x1B[37m Parameter CLOCK_FREQ bound to: 64'b0000000000000000000000000000000000000101111101011110000100000000#x1B[39m
#x1B[37m Parameter TIMEBASE bound to: 10000000000000 - type: long integer#x1B[39m
#x1B[37m Parameter CONFIG bound to: 128'b00000000000000000000000000010100000000000000000000000000000011000000000000000000000000000001010000000000000000000000000000001100#x1B[39m
#x1B[34mRTL report: "TimingToCycles(freq, freq): delay=100.000000 ms" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:109]#x1B[39m
#x1B[34mRTL report: "TimingToCycles(time, freq): period=10.000000 ns -- 0.000000 fs" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:118]#x1B[39m
#x1B[34msynthesizing module 'Counter' [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[37m Parameter MODULO bound to: 10000000 - type: integer#x1B[39m
#x1B[37m Parameter BITS bound to: 1 - type: integer#x1B[39m
#x1B[34mdone synthesizing module 'Counter' (0#1) [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[34msynthesizing module 'Counter__parameterized0' [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[37m Parameter MODULO bound to: 10 - type: integer#x1B[39m
#x1B[37m Parameter BITS bound to: 4 - type: integer#x1B[39m
#x1B[34mdone synthesizing module 'Counter__parameterized0' (0#1) [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[34msynthesizing module 'Counter__parameterized1' [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[37m Parameter MODULO bound to: 6 - type: integer#x1B[39m
#x1B[37m Parameter BITS bound to: 4 - type: integer#x1B[39m
#x1B[34mdone synthesizing module 'Counter__parameterized1' (0#1) [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[34mRTL report: "TimingToCycles(freq, freq): delay=100.000000 ms" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:109]#x1B[39m
#x1B[34mRTL report: "TimingToCycles(time, freq): period=10.000000 ns -- 0.000000 fs" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:118]#x1B[39m
#x1B[34mdone synthesizing module 'Stopwatch' (0#1) [C:/Git/PLC2/Training/StopWatch/src/StopWatch.vhdl:28]#x1B[39m
#x1B[34msynthesizing module 'seg7_Display' [C:/Git/PLC2/Training/StopWatch/src/seg7_Display.vhdl:27]#x1B[39m
#x1B[37m Parameter CLOCK_FREQ bound to: 64'b0000000000000000000000000000000000000101111101011110000100000000#x1B[39m
#x1B[37m Parameter DIGITS bound to: 4 - type: integer#x1B[39m
#x1B[34mRTL report: "TimingToCycles(freq, freq): delay=1.000000 ms" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:109]#x1B[39m
#x1B[34mRTL report: "TimingToCycles(time, freq): period=10.000000 ns -- 0.000000 fs" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:118]#x1B[39m
#x1B[34msynthesizing module 'Counter__parameterized2' [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[37m Parameter MODULO bound to: 100000 - type: integer#x1B[39m
#x1B[34mdone synthesizing module 'Counter__parameterized2' (0#1) [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[34msynthesizing module 'Counter__parameterized3' [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[37m Parameter MODULO bound to: 4 - type: integer#x1B[39m
#x1B[37m Parameter BITS bound to: 2 - type: integer#x1B[39m
#x1B[34mdone synthesizing module 'Counter__parameterized3' (0#1) [C:/Git/PLC2/Training/StopWatch/src/Counter.vhdl:24]#x1B[39m
#x1B[34msynthesizing module 'seg7_Encoder' [C:/Git/PLC2/Training/StopWatch/src/seg7_Encoder.vhdl:17]#x1B[39m
#x1B[34mdefault block is never used [C:/Git/PLC2/Training/StopWatch/src/seg7_Encoder.vhdl:23]#x1B[39m
#x1B[34mdone synthesizing module 'seg7_Encoder' (0#1) [C:/Git/PLC2/Training/StopWatch/src/seg7_Encoder.vhdl:17]#x1B[39m
#x1B[34mRTL report: "TimingToCycles(freq, freq): delay=1.000000 ms" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:109]#x1B[39m
#x1B[34mRTL report: "TimingToCycles(time, freq): period=10.000000 ns -- 0.000000 fs" [C:/Git/PLC2/Training/StopWatch/src/Utilities.pkg.vhdl:118]#x1B[39m
#x1B[34mdone synthesizing module 'seg7_Display' (0#1) [C:/Git/PLC2/Training/StopWatch/src/seg7_Display.vhdl:27]#x1B[39m
#x1B[34mdone synthesizing module 'toplevel' (0#1) [C:/Git/PLC2/Training/StopWatch/src/toplevel.WithTiming.vhdl:26]#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1316.539 ; gain = 606.094#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Handling Custom Attributes#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1316.539 ; gain = 606.094#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[94m---------------------------------------------------------------------------------#x1B[39m
#x1B[94mFinished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1316.539 ; gain = 606.094#x1B[39m
#x1B[94m---------------------------------------------------------------------------------#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1316.539 ; gain = 0.000#x1B[39m
#x1B[34mAnalyzing 11 Unisim elements for replacement#x1B[39m
#x1B[34mUnisim Transformation completed in 0 CPU seconds#x1B[39m
#x1B[34mPreparing netlist for logic optimization#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mProcessing XDC Constraints#x1B[39m
#x1B[90mInitializing timing engine#x1B[39m
#x1B[90mParsing XDC File [C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/synth_1/dont_touch.xdc]#x1B[39m
#x1B[90mFinished Parsing XDC File [C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/synth_1/dont_touch.xdc]#x1B[39m
#x1B[90mCompleted Processing XDC Constraints#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1389.562 ; gain = 0.000#x1B[39m
#x1B[34mUnisim Transformation Summary:#x1B[39m
#x1B[90m A total of 10 instances were transformed.#x1B[39m
#x1B[90m FD => FDRE: 10 instances#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mConstraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1389.562 ; gain = 0.000#x1B[39m
#x1B[34mIncremental synthesis strategy off#x1B[39m
#x1B[90m---------------------------------------------------------------------------------#x1B[39m
#x1B[90mFinished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1389.562 ; gain = 679.117#x1B[39m
#x1B[90m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Loading Part and Timing Information#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[97mLoading part: xc7a100tcsg324-1#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1389.562 ; gain = 679.117#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Applying 'set_property' XDC Constraints#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1389.562 ; gain = 679.117#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[34minferred FSM for state register 'State_reg' in module 'Stopwatch'#x1B[39m
#x1B[90m---------------------------------------------------------------------------------------------------#x1B[39m
#x1B[90m State | New Encoding | Previous Encoding#x1B[39m
#x1B[90m---------------------------------------------------------------------------------------------------#x1B[39m
#x1B[90m st_reset | 0001 | 00#x1B[39m
#x1B[90m st_idle | 0010 | 01#x1B[39m
#x1B[90m st_counting | 0100 | 10#x1B[39m
#x1B[90m st_pause | 1000 | 11#x1B[39m
#x1B[90m---------------------------------------------------------------------------------------------------#x1B[39m
#x1B[34mencoded FSM with state register 'State_reg' using encoding 'one-hot' in module 'Stopwatch'#x1B[39m
#x1B[94m---------------------------------------------------------------------------------#x1B[39m
#x1B[94mFinished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1389.562 ; gain = 679.117#x1B[39m
#x1B[94m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart RTL Component Statistics#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[37mDetailed RTL Component Info :#x1B[39m
#x1B[37m+---Adders :#x1B[39m
#x1B[37m 2 Input 9 Bit Adders := 2#x1B[39m
#x1B[37m 2 Input 4 Bit Adders := 2#x1B[39m
#x1B[37m 2 Input 3 Bit Adders := 2#x1B[39m
#x1B[37m 2 Input 2 Bit Adders := 1#x1B[39m
#x1B[37m+---Registers :#x1B[39m
#x1B[37m 9 Bit Registers := 2#x1B[39m
#x1B[37m 8 Bit Registers := 2#x1B[39m
#x1B[37m 4 Bit Registers := 2#x1B[39m
#x1B[37m 3 Bit Registers := 2#x1B[39m
#x1B[37m 2 Bit Registers := 1#x1B[39m
#x1B[37m 1 Bit Registers := 3#x1B[39m
#x1B[37m+---Muxes :#x1B[39m
#x1B[37m 4 Input 4 Bit Muxes := 2#x1B[39m
#x1B[37m 2 Input 4 Bit Muxes := 1#x1B[39m
#x1B[37m 2 Input 1 Bit Muxes := 5#x1B[39m
#x1B[37m 4 Input 1 Bit Muxes := 1#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished RTL Component Statistics#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Part Resource Summary#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[37mPart Resources:#x1B[39m
#x1B[37mDSPs: 240 (col length:80)#x1B[39m
#x1B[37mBRAMs: 270 (col length: RAMB18 80 RAMB36 40)#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Part Resource Summary#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Cross Boundary and Area Optimization#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[93mParallel synthesis criteria is not met#x1B[39m
#x1B[93mSequential element (gen[0].Sync/FF2) is unused and will be removed from module sync_Bits_Xilinx__2.#x1B[39m
#x1B[93mSequential element (gen[0].Sync/FF2) is unused and will be removed from module sync_Bits_Xilinx.#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1389.562 ; gain = 679.117#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Applying XDC Timing Constraints#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Applying XDC Timing Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1522.004 ; gain = 811.559#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Timing Optimization#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Timing Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1522.227 ; gain = 811.781#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Technology Mapping#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Technology Mapping : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1550.859 ; gain = 840.414#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart IO Insertion#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Flattening Before IO Insertion#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Flattening Before IO Insertion#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Final Netlist Cleanup#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Final Netlist Cleanup#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished IO Insertion : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1766.477 ; gain = 1056.031#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Renaming Generated Instances#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Renaming Generated Instances : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1766.477 ; gain = 1056.031#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Rebuilding User Hierarchy#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Rebuilding User Hierarchy : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1766.477 ; gain = 1056.031#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Renaming Generated Ports#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Renaming Generated Ports : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1766.477 ; gain = 1056.031#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Handling Custom Attributes#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Handling Custom Attributes : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1766.477 ; gain = 1056.031#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Renaming Generated Nets#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Renaming Generated Nets : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1766.477 ; gain = 1056.031#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mStart Writing Synthesis Report#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[39m#x1B[39m
#x1B[33mReport BlackBoxes:#x1B[39m
#x1B[97m+-+--------------+----------+#x1B[39m
#x1B[97m| |BlackBox name |Instances |#x1B[39m
#x1B[97m+-+--------------+----------+#x1B[39m
#x1B[97m+-+--------------+----------+#x1B[39m
#x1B[39m#x1B[39m
#x1B[33mReport Cell Usage:#x1B[39m
#x1B[97m+------+-----------+------+#x1B[39m
#x1B[97m| |Cell |Count |#x1B[39m
#x1B[97m+------+-----------+------+#x1B[39m
#x1B[97m|1 |BUFG | 3|#x1B[39m
#x1B[97m|2 |CARRY4 | 11|#x1B[39m
#x1B[97m|3 |LUT1 | 9|#x1B[39m
#x1B[97m|4 |LUT2 | 13|#x1B[39m
#x1B[97m|5 |LUT3 | 14|#x1B[39m
#x1B[97m|6 |LUT4 | 22|#x1B[39m
#x1B[97m|7 |LUT5 | 8|#x1B[39m
#x1B[97m|8 |LUT6 | 14|#x1B[39m
#x1B[97m|9 |MMCME2_ADV | 1|#x1B[39m
#x1B[97m|10 |FD | 8|#x1B[39m
#x1B[97m|11 |FDRE | 81|#x1B[39m
#x1B[97m|12 |FDSE | 12|#x1B[39m
#x1B[97m|13 |IBUF | 3|#x1B[39m
#x1B[97m|14 |OBUF | 16|#x1B[39m
#x1B[97m+------+-----------+------+#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[36mFinished Writing Synthesis Report : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1766.477 ; gain = 1056.031#x1B[39m
#x1B[36m---------------------------------------------------------------------------------#x1B[39m
#x1B[90mSynthesis finished with 0 errors, 0 critical warnings and 3 warnings.#x1B[39m
#x1B[90mSynthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1766.477 ; gain = 983.008#x1B[39m
#x1B[90mSynthesis Optimization Complete : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1766.477 ; gain = 1056.031#x1B[39m
#x1B[34mTranslating synthesized netlist#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1766.477 ; gain = 0.000#x1B[39m
#x1B[34mAnalyzing 20 Unisim elements for replacement#x1B[39m
#x1B[34mUnisim Transformation completed in 0 CPU seconds#x1B[39m
#x1B[34mPreparing netlist for logic optimization#x1B[39m
#x1B[34mPushed 0 inverter(s) to 0 load pin(s).#x1B[39m
#x1B[90mNetlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1779.379 ; gain = 0.000#x1B[39m
#x1B[34mUnisim Transformation Summary:#x1B[39m
#x1B[90m A total of 8 instances were transformed.#x1B[39m
#x1B[90m FD => FDRE: 8 instances#x1B[39m
#x1B[39m#x1B[39m
#x1B[90mSynth Design complete | Checksum: 653e62d0#x1B[39m
#x1B[34mReleasing license: Synthesis#x1B[39m
#x1B[90m66 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.#x1B[39m
#x1B[92msynth_design completed successfully#x1B[39m
#x1B[90msynth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:34 . Memory (MB): peak = 1779.379 ; gain = 1271.582#x1B[39m
#x1B[90mWrite ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1779.379 ; gain = 0.000#x1B[39m
#x1B[34mThe checkpoint 'C:/Git/PLC2/Training/StopWatch/project/4_WithTiming.runs/synth_1/toplevel.dcp' has been generated.#x1B[39m
#x1B[34mExecuting command : report_utilization -file toplevel_utilization_synth.rpt -pb toplevel_utilization_synth.pb#x1B[39m
#x1B[34mExiting Vivado at Thu Jun 12 18:38:58 2025...#x1B[39m
Standard Error
--------------------------------- Captured Err ---------------------------------