Code Coverage of pyEDAA.ProjectModel: 72%

Files Functions Classes

coverage.py v7.11.0, created at 2025-10-18 17:08 +0000

File class statements missing excluded branches partial coverage
pyEDAA/ProjectModel/Attributes.py KeyValueAttribute 4 0 0 0 0 100%
pyEDAA/ProjectModel/Attributes.py (no class) 10 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoFileMixIn 1 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py ConstraintFile 2 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VerilogSourceFile 2 2 0 0 0 0%
pyEDAA/ProjectModel/Xilinx/Vivado.py VHDLSourceFile 2 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile 60 12 0 46 4 81%
pyEDAA/ProjectModel/Xilinx/Vivado.py XDCConstraintFile 3 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py (no class) 63 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Attribute 7 1 0 6 1 85%
pyEDAA/ProjectModel/__init__.py FileType 9 0 0 2 0 100%
pyEDAA/ProjectModel/__init__.py File 84 23 0 42 16 67%
pyEDAA/ProjectModel/__init__.py VHDLSourceFile 44 18 2 18 2 61%
pyEDAA/ProjectModel/__init__.py VerilogMixIn 6 0 0 4 0 100%
pyEDAA/ProjectModel/__init__.py SystemVerilogMixIn 6 0 0 4 0 100%
pyEDAA/ProjectModel/__init__.py VerilogBaseFile 2 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py SystemRDLSourceFile 8 8 0 4 0 0%
pyEDAA/ProjectModel/__init__.py FileSet 196 71 4 122 28 60%
pyEDAA/ProjectModel/__init__.py VHDLLibrary 76 43 2 44 7 38%
pyEDAA/ProjectModel/__init__.py Design 145 68 0 84 18 49%
pyEDAA/ProjectModel/__init__.py Project 61 20 0 22 9 65%
pyEDAA/ProjectModel/__init__.py (no class) 426 0 0 0 0 100%
Total   1217 266 8 398 85 72%

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43 empty classes skipped.