Code Coverage of pyEDAA.ProjectModel

		Statements				Branches			Total
File	class	coverage	statements	missing	excluded	coverage	branches	partial	coverage
pyEDAA/ProjectModel/Attributes.py	KeyValueAttribute	100%	4	0	0	100%	0	0	100%
pyEDAA/ProjectModel/Attributes.py	(no class)	100%	9	0	0	100%	0	0	100%
pyEDAA/ProjectModel/Xilinx/Vivado.py	VivadoFileMixIn	100%	1	0	0	100%	0	0	100%
pyEDAA/ProjectModel/Xilinx/Vivado.py	ConstraintFile	100%	2	0	0	100%	0	0	100%
pyEDAA/ProjectModel/Xilinx/Vivado.py	VerilogSourceFile	0%	2	2	0	100%	0	0	0%
pyEDAA/ProjectModel/Xilinx/Vivado.py	VHDLSourceFile	100%	2	0	0	100%	0	0	100%
pyEDAA/ProjectModel/Xilinx/Vivado.py	VivadoProjectFile	80%	60	12	0	83%	46	4	81%
pyEDAA/ProjectModel/Xilinx/Vivado.py	XDCConstraintFile	100%	3	0	0	100%	0	0	100%
pyEDAA/ProjectModel/Xilinx/Vivado.py	(no class)	100%	62	0	0	100%	0	0	100%
pyEDAA/ProjectModel/__init__.py	Attribute	86%	7	1	0	83%	6	1	85%
pyEDAA/ProjectModel/__init__.py	FileType	100%	9	0	0	100%	2	0	100%
pyEDAA/ProjectModel/__init__.py	File	73%	84	23	0	57%	42	16	67%
pyEDAA/ProjectModel/__init__.py	VHDLSourceFile	59%	44	18	2	67%	18	2	61%
pyEDAA/ProjectModel/__init__.py	VerilogMixIn	100%	6	0	0	100%	4	0	100%
pyEDAA/ProjectModel/__init__.py	SystemVerilogMixIn	100%	6	0	0	100%	4	0	100%
pyEDAA/ProjectModel/__init__.py	VerilogBaseFile	100%	2	0	0	100%	0	0	100%
pyEDAA/ProjectModel/__init__.py	SystemRDLSourceFile	0%	8	8	0	0%	4	0	0%
pyEDAA/ProjectModel/__init__.py	FileSet	64%	196	71	4	54%	122	28	60%
pyEDAA/ProjectModel/__init__.py	VHDLLibrary	44%	77	43	2	30%	44	7	39%
pyEDAA/ProjectModel/__init__.py	Design	53%	145	68	0	43%	84	18	49%
pyEDAA/ProjectModel/__init__.py	Project	67%	61	20	0	59%	22	9	65%
pyEDAA/ProjectModel/__init__.py	(no class)	100%	370	0	0	100%	0	0	100%
Total		77%	1160	266	8	55%	398	85	71%

No items found using the specified filter.

43 empty classes skipped.

Code Coverage of pyEDAA.ProjectModel: 71%