Code Coverage of pyEDAA.ProjectModel: 71%

Files Functions Classes

coverage.py v7.6.7, created at 2024-11-20 23:18 +0000

File function statements missing excluded branches partial coverage
pyEDAA/ProjectModel/Attributes.py KeyValueAttribute.__init__ 2 0 0 0 0 100%
pyEDAA/ProjectModel/Attributes.py KeyValueAttribute.__getitem__ 1 0 0 0 0 100%
pyEDAA/ProjectModel/Attributes.py KeyValueAttribute.__setitem__ 1 0 0 0 0 100%
pyEDAA/ProjectModel/Attributes.py (no function) 10 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoFileMixIn._registerAttributes 1 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py ConstraintFile._registerAttributes 2 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VerilogSourceFile._registerAttributes 2 2 0 0 0 0%
pyEDAA/ProjectModel/Xilinx/Vivado.py VHDLSourceFile._registerAttributes 2 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile.__init__ 2 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile.ProjectModel 1 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile.Parse 8 3 0 2 1 60%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseRootElement 4 0 0 4 1 88%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseFileSets 3 0 0 4 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseFileSet 8 0 0 8 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseFile 11 5 0 8 1 47%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseVHDLFile 15 1 0 14 1 93%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseDefaultFile 1 1 0 0 0 0%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseXDCFile 1 0 0 0 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseVerilogFile 1 1 0 0 0 0%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseXCIFile 1 1 0 0 0 0%
pyEDAA/ProjectModel/Xilinx/Vivado.py VivadoProjectFile._ParseFileSetConfig 4 0 0 6 0 100%
pyEDAA/ProjectModel/Xilinx/Vivado.py (no function) 53 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Attribute.resolve 7 5 0 6 1 23%
pyEDAA/ProjectModel/__init__.py FileType.__init__ 2 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileType.__new__ 3 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileType.__getattr__ 3 0 0 2 0 100%
pyEDAA/ProjectModel/__init__.py FileType.__contains__ 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py File.__init__ 23 1 0 10 1 94%
pyEDAA/ProjectModel/__init__.py File._registerAttributes 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py File.FileType 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py File.Path 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py File.ResolvedPath 8 3 0 6 3 57%
pyEDAA/ProjectModel/__init__.py File.Project 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py File.Project 3 0 0 2 1 80%
pyEDAA/ProjectModel/__init__.py File.Design 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py File.Design 7 2 0 6 2 54%
pyEDAA/ProjectModel/__init__.py File.FileSet 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py File.FileSet 2 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py File.Validate 16 8 0 12 6 50%
pyEDAA/ProjectModel/__init__.py File.__len__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py File.__getitem__ 11 5 0 2 1 54%
pyEDAA/ProjectModel/__init__.py File.__setitem__ 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py File.__delitem__ 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py File.__str__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py VHDLSourceFile.__init__ 21 13 2 10 2 39%
pyEDAA/ProjectModel/__init__.py VHDLSourceFile.Validate 9 4 0 0 0 56%
pyEDAA/ProjectModel/__init__.py VHDLSourceFile.VHDLLibrary 5 0 0 4 0 100%
pyEDAA/ProjectModel/__init__.py VHDLSourceFile.VHDLLibrary 2 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py VHDLSourceFile.VHDLVersion 5 0 0 4 0 100%
pyEDAA/ProjectModel/__init__.py VHDLSourceFile.VHDLVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py VHDLSourceFile.__repr__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py VerilogMixIn.VerilogVersion 5 0 0 4 0 100%
pyEDAA/ProjectModel/__init__.py VerilogMixIn.VerilogVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py SystemVerilogMixIn.SVVersion 5 0 0 4 0 100%
pyEDAA/ProjectModel/__init__.py SystemVerilogMixIn.SVVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py VerilogBaseFile.__init__ 2 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py SystemRDLSourceFile.__init__ 2 2 0 0 0 0%
pyEDAA/ProjectModel/__init__.py SystemRDLSourceFile.SystemRDLVersion 5 5 0 4 0 0%
pyEDAA/ProjectModel/__init__.py SystemRDLSourceFile.SystemRDLVersion 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.__init__ 24 0 0 6 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.Name 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.Name 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.TopLevel 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.TopLevel 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.Project 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.Project 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.Design 5 1 0 4 1 78%
pyEDAA/ProjectModel/__init__.py FileSet.Design 5 2 0 4 1 44%
pyEDAA/ProjectModel/__init__.py FileSet.Directory 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.Directory 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.ResolvedPath 13 6 0 10 4 48%
pyEDAA/ProjectModel/__init__.py FileSet.Parent 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.Parent 2 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.FileSets 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.Files 21 15 0 22 3 30%
pyEDAA/ProjectModel/__init__.py FileSet.AddFileSet 8 3 0 6 3 57%
pyEDAA/ProjectModel/__init__.py FileSet.AddFileSets 2 0 0 2 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.FileSetCount 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.TotalFileSetCount 4 4 0 2 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.AddFile 11 2 4 6 1 82%
pyEDAA/ProjectModel/__init__.py FileSet.AddFiles 2 0 0 2 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.FileCount 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.TotalFileCount 4 4 0 2 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.Validate 20 10 0 16 8 50%
pyEDAA/ProjectModel/__init__.py FileSet.GetOrCreateVHDLLibrary 9 0 0 4 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.VHDLLibrary 7 3 0 6 1 54%
pyEDAA/ProjectModel/__init__.py FileSet.VHDLLibrary 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.VHDLVersion 7 1 0 6 1 85%
pyEDAA/ProjectModel/__init__.py FileSet.VHDLVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.VerilogVersion 7 1 0 6 1 85%
pyEDAA/ProjectModel/__init__.py FileSet.VerilogVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.SVVersion 7 1 0 6 1 85%
pyEDAA/ProjectModel/__init__.py FileSet.SVVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py FileSet.SRDLVersion 7 7 0 6 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.SRDLVersion 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.__len__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py FileSet.__getitem__ 6 3 0 2 1 50%
pyEDAA/ProjectModel/__init__.py FileSet.__setitem__ 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py FileSet.__delitem__ 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py FileSet.__str__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.__init__ 20 2 0 8 2 86%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.Name 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.Project 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.Project 7 2 0 6 3 62%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.Design 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.Design 14 14 0 12 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.Files 2 2 0 2 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.VHDLVersion 5 1 0 4 1 78%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.VHDLVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.AddDependency 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.AddFile 4 2 2 2 1 50%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.AddFiles 4 4 0 4 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.FileCount 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.__len__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.__getitem__ 6 6 0 2 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.__setitem__ 3 3 0 2 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.__delitem__ 3 3 0 2 0 0%
pyEDAA/ProjectModel/__init__.py VHDLLibrary.__str__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Design.__init__ 17 0 0 2 0 100%
pyEDAA/ProjectModel/__init__.py Design.Name 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.Name 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Design.TopLevel 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Design.TopLevel 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Design.Project 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.Project 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.Directory 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.Directory 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.ResolvedPath 8 3 0 6 3 57%
pyEDAA/ProjectModel/__init__.py Design.DefaultFileSet 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.DefaultFileSet 9 9 0 8 0 0%
pyEDAA/ProjectModel/__init__.py Design.FileSets 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.Files 13 4 0 12 1 72%
pyEDAA/ProjectModel/__init__.py Design.Validate 23 11 0 16 7 54%
pyEDAA/ProjectModel/__init__.py Design.VHDLLibraries 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.VHDLVersion 5 1 0 4 1 78%
pyEDAA/ProjectModel/__init__.py Design.VHDLVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.VerilogVersion 5 1 0 4 1 78%
pyEDAA/ProjectModel/__init__.py Design.VerilogVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.SVVersion 5 1 0 4 1 78%
pyEDAA/ProjectModel/__init__.py Design.SVVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Design.SRDLVersion 5 5 0 4 0 0%
pyEDAA/ProjectModel/__init__.py Design.SRDLVersion 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Design.ExternalVHDLLibraries 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Design.AddFileSet 9 9 0 6 0 0%
pyEDAA/ProjectModel/__init__.py Design.AddFileSets 2 2 0 2 0 0%
pyEDAA/ProjectModel/__init__.py Design.FileSetCount 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Design.TotalFileSetCount 4 4 0 2 0 0%
pyEDAA/ProjectModel/__init__.py Design.AddFile 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py Design.AddFiles 2 2 0 2 0 0%
pyEDAA/ProjectModel/__init__.py Design.AddVHDLLibrary 4 4 0 4 0 0%
pyEDAA/ProjectModel/__init__.py Design.__len__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Design.__getitem__ 6 3 0 2 1 50%
pyEDAA/ProjectModel/__init__.py Design.__setitem__ 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py Design.__delitem__ 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py Design.__str__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Project.__init__ 8 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.Name 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.RootDirectory 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.RootDirectory 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.ResolvedPath 4 0 0 2 0 100%
pyEDAA/ProjectModel/__init__.py Project.Designs 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.DefaultDesign 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.Validate 21 10 0 14 6 54%
pyEDAA/ProjectModel/__init__.py Project.DesignCount 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Project.VHDLVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.VHDLVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.VerilogVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.VerilogVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.SVVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.SVVersion 1 0 0 0 0 100%
pyEDAA/ProjectModel/__init__.py Project.SRDLVersion 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Project.SRDLVersion 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Project.__len__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py Project.__getitem__ 6 3 0 2 1 50%
pyEDAA/ProjectModel/__init__.py Project.__setitem__ 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py Project.__delitem__ 3 1 0 2 1 60%
pyEDAA/ProjectModel/__init__.py Project.__str__ 1 1 0 0 0 0%
pyEDAA/ProjectModel/__init__.py (no function) 426 0 0 0 0 100%
Total   1204 274 8 398 85 71%

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