Unittest Summary Report

Testsuite / Testcase

Testcases

Skipped

Errored

Failed

Passed

Runtime (HH:MM:SS.sss)

✅pyEDAA.ProjectModel

110

1

0

0

109

00:00:00.292

  ✅DependencyScan

1

1

0

0

0

00:00:00.001

    ✅VHDL

1

1

0

0

0

00:00:00.001

      ⚠️test_VHDLLibrary

00:00:00.001

  ✅Design

16

0

0

0

16

00:00:00.021

    ✅Attributes

6

0

0

0

6

00:00:00.006

    ✅Instantiate

3

0

0

0

3

00:00:00.005

    ✅Properties

6

0

0

0

6

00:00:00.008

    ✅Validate

1

0

0

0

1

00:00:00.002

  ✅File

21

0

0

0

21

00:00:00.024

    ✅AttributeResolution

4

0

0

0

4

00:00:00.005

    ✅Attributes

6

0

0

0

6

00:00:00.006

    ✅Instantiate

5

0

0

0

5

00:00:00.005

    ✅Properties

5

0

0

0

5

00:00:00.006

    ✅Validate

1

0

0

0

1

00:00:00.002

  ✅FileSet

36

0

0

0

36

00:00:00.046

    ✅AttributeResolution

2

0

0

0

2

00:00:00.002

    ✅Attributes

6

0

0

0

6

00:00:00.008

    ✅FileFilter

3

0

0

0

3

00:00:00.005

    ✅Instantiate

5

0

0

0

5

00:00:00.005

    ✅Operations

7

0

0

0

7

00:00:00.007

    ✅Properties

12

0

0

0

12

00:00:00.016

    ✅Validate

1

0

0

0

1

00:00:00.003

  ✅Files

15

0

0

0

15

00:00:00.016

    ✅SystemVerilogFile

4

0

0

0

4

00:00:00.004

    ✅VHDLFile

7

0

0

0

7

00:00:00.008

    ✅VerilogFile

4

0

0

0

4

00:00:00.004

  ✅Project

12

0

0

0

12

00:00:00.014

    ✅Attributes

6

0

0

0

6

00:00:00.006

    ✅Instantiate

3

0

0

0

3

00:00:00.004

    ✅Properties

2

0

0

0

2

00:00:00.002

    ✅Validate

1

0

0

0

1

00:00:00.002

  ✅VHDLLibrary

8

0

0

0

8

00:00:00.008

    ✅Instantiate

8

0

0

0

8

00:00:00.008

  ✅VivadoProject

1

0

0

0

1

00:00:00.162

    ✅FileSets

1

0

0

0

1

00:00:00.162

✅ PASSED

110

1

0

0

109

00:00:00.292


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