Unittest Summary Report

Testsuite / Testcase	Testcases	Skipped	Errored	Failed	Passed	Runtime (HH:MM:SS.sss)
✅TestsuiteSummary	109	1	0	0	108	00:00:00.298
✅unit	109	1	0	0	108	00:00:00.298
✅DependencyScan	1	1	0	0	0	00:00:00.001
✅VHDL	1	1	0	0	0	00:00:00.001
⚠️test_VHDLLibrary						00:00:00.001
✅Design	16	0	0	0	16	00:00:00.042
✅Attributes	6	0	0	0	6	00:00:00.014
✅Instantiate	3	0	0	0	3	00:00:00.006
✅Properties	6	0	0	0	6	00:00:00.019
✅Validate	1	0	0	0	1	00:00:00.003
✅File	21	0	0	0	21	00:00:00.049
✅AttributeResolution	4	0	0	0	4	00:00:00.010
✅Attributes	6	0	0	0	6	00:00:00.017
✅Instantiate	5	0	0	0	5	00:00:00.011
✅Properties	5	0	0	0	5	00:00:00.007
✅Validate	1	0	0	0	1	00:00:00.004
✅FileSet	35	0	0	0	35	00:00:00.067
✅AttributeResolution	2	0	0	0	2	00:00:00.003
✅Attributes	6	0	0	0	6	00:00:00.009
✅FileFilter	2	0	0	0	2	00:00:00.005
✅Instantiate	5	0	0	0	5	00:00:00.007
✅Operations	7	0	0	0	7	00:00:00.014
✅Properties	12	0	0	0	12	00:00:00.025
✅Validate	1	0	0	0	1	00:00:00.004
✅Files	15	0	0	0	15	00:00:00.034
✅SystemVerilogFile	4	0	0	0	4	00:00:00.009
✅VHDLFile	7	0	0	0	7	00:00:00.017
✅VerilogFile	4	0	0	0	4	00:00:00.008
✅Project	12	0	0	0	12	00:00:00.025
✅Attributes	6	0	0	0	6	00:00:00.011
✅Instantiate	3	0	0	0	3	00:00:00.006
✅Properties	2	0	0	0	2	00:00:00.004
✅Validate	1	0	0	0	1	00:00:00.004
✅VHDLLibrary	8	0	0	0	8	00:00:00.013
✅Instantiate	8	0	0	0	8	00:00:00.013
✅VivadoProject	1	0	0	0	1	00:00:00.067
✅FileSets	1	0	0	0	1	00:00:00.067
✅ PASSED	109	1	0	0	108	00:00:00.298

Legend: ✅ passed, ❌ failed, ⚠️ skipped, ➖ excluded, ❗ errored, ⛔ setup error, 🚫 aborted, ❓ unknown

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Unittest report generated with pytest and visualized by pyTooling.Sphinx.