Unittest Summary Report

Testsuite / Testcase	Testcases	Skipped	Errored	Failed	Passed	Runtime (HH:MM:SS.sss)
✅TestsuiteSummary	109	1	0	0	108	00:00:00.325
✅DependencyScan	1	1	0	0	0	00:00:00.001
✅VHDL	1	1	0	0	0	00:00:00.001
⚠️test_VHDLLibrary						00:00:00.001
✅Design	16	0	0	0	16	00:00:00.049
✅Attributes	6	0	0	0	6	00:00:00.006
✅Instantiate	3	0	0	0	3	00:00:00.011
✅Properties	6	0	0	0	6	00:00:00.020
✅Validate	1	0	0	0	1	00:00:00.012
✅File	21	0	0	0	21	00:00:00.031
✅AttributeResolution	4	0	0	0	4	00:00:00.009
✅Attributes	6	0	0	0	6	00:00:00.007
✅Instantiate	5	0	0	0	5	00:00:00.004
✅Properties	5	0	0	0	5	00:00:00.006
✅Validate	1	0	0	0	1	00:00:00.005
✅FileSet	35	0	0	0	35	00:00:00.043
✅AttributeResolution	2	0	0	0	2	00:00:00.002
✅Attributes	6	0	0	0	6	00:00:00.006
✅FileFilter	2	0	0	0	2	00:00:00.002
✅Instantiate	5	0	0	0	5	00:00:00.012
✅Operations	7	0	0	0	7	00:00:00.007
✅Properties	12	0	0	0	12	00:00:00.012
✅Validate	1	0	0	0	1	00:00:00.002
✅Files	15	0	0	0	15	00:00:00.024
✅SystemVerilogFile	4	0	0	0	4	00:00:00.003
✅VHDLFile	7	0	0	0	7	00:00:00.017
✅VerilogFile	4	0	0	0	4	00:00:00.004
✅Project	12	0	0	0	12	00:00:00.016
✅Attributes	6	0	0	0	6	00:00:00.004
✅Instantiate	3	0	0	0	3	00:00:00.003
✅Properties	2	0	0	0	2	00:00:00.002
✅Validate	1	0	0	0	1	00:00:00.007
✅VHDLLibrary	8	0	0	0	8	00:00:00.005
✅Instantiate	8	0	0	0	8	00:00:00.005
✅VivadoProject	1	0	0	0	1	00:00:00.156
✅FileSets	1	0	0	0	1	00:00:00.156
✅ PASSED	109	1	0	0	108	00:00:00.325

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Unittest report generated with pytest and visualized by sphinx-reports.